The influence and explanation of fringing-induced barrier lowering on sub-100 nm MOSFETs with high-k gate dielectrics

doi:10.1088/1674-1056/21/5/057305

Abstract The fringing-induced barrier lowering (FIBL) effect of sub-100 nm MOSFETs with high-k gate dielectrics is investigated using a two-dimensional device simulator. An equivalent capacitance theory is proposed to explain the physics mechanism of the FIBL effect. The FIBL effect is enhanced and the short channel performance is degraded with increasing capacitance. Based on equivalent capacitance theory, the influences of channel length, junction depth, gate/lightly doped drain (LDD) overlap length, spacer material and spacer width on FIBL is thoroughly investigated. A stack gate dielectric is presented to suppress the FIBL effect.

Keywords: high-k gate dielectric fringing-induced barrier lowering stack gate dielectric MOSFET

Received: 17 October 2011
Revised: 27 April 2012
Accepted manuscript online:

PACS:	73.40.Qv	(Metal-insulator-semiconductor structures (including semiconductor-to-insulator))
	73.61.Ng	(Insulators)

Fund: Project supported by the National Natural Science Foundation of China (Grant Nos. 60936005 and 61076097), the Cultivation Fund of the Key Scientific and Technical Innovation Project of Ministry of Education of China (Grant No. 708083), and the Fundamental Research Funds for the Central Universities, China (Grant No. 20110203110012).

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Ma Fei(马飞), Liu Hong-Xia(刘红侠), Kuang Qian-Wei(匡潜玮), and Fan Ji-Bin(樊继斌) The influence and explanation of fringing-induced barrier lowering on sub-100 nm MOSFETs with high-k gate dielectrics 2012 Chin. Phys. B 21 057305

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The influence and explanation of fringing-induced barrier lowering on sub-100 nm MOSFETs with high-k gate dielectrics

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