Please wait a minute...
Chin. Phys. B, 2016, Vol. 25(4): 048502    DOI: 10.1088/1674-1056/25/4/048502
INTERDISCIPLINARY PHYSICS AND RELATED AREAS OF SCIENCE AND TECHNOLOGY Prev   Next  

Ultra-low specific on-resistance high-voltage vertical double diffusion metal-oxide-semiconductor field-effect transistor with continuous electron accumulation layer

Da Ma(马达)1, Xiao-Rong Luo(罗小蓉)1,2, Jie Wei(魏杰)1, Qiao Tan(谭桥)1, Kun Zhou(周坤)1, Jun-Feng Wu(吴俊峰)1
1 State Key Laboratory of Electronic Thin Films and Integrated Devices. University of Electronic Science and Technology of China, Chengdu 610054, China;
2 Science and Technology on Analog Integrated Circuit Laboratory, Chongqing 400060, China
Abstract  A new ultra-low specific on-resistance (Ron,sp) vertical double diffusion metal-oxide-semiconductor field-effect transistor (VDMOS) with continuous electron accumulation (CEA) layer, denoted as CEA-VDMOS, is proposed and its new current transport mechanism is investigated. It features a trench gate directly extended to the drain, which includes two PN junctions. In on-state, the electron accumulation layers are formed along the sides of the extended gate and introduce two continuous low-resistance current paths from the source to the drain in a cell pitch. This mechanism not only dramatically reduces the Ron,sp but also makes the Ron,sp almost independent of the n-pillar doping concentration (Nn). In off-state, the depletion between the n-pillar and p-pillar within the extended trench gate increases the Nn, and further reduces the Ron,sp. Especially, the two PN junctions within the trench gate support a high gate-drain voltage in the off-state and on-state, respectively. However, the extended gate increases the gate capacitance and thus weakens the dynamic performance to some extent. Therefore, the CEA-VDMOS is more suitable for low and medium frequencies application. Simulation indicates that the CEA-VDMOS reduces the Ron,sp by 80% compared with the conventional super-junction VDMOS (CSJ-VDMOS) at the same high breakdown voltage (BV).
Keywords:  electron accumulation layer      PN junctions      low specific on-resistance      high breakdown voltage     
Received:  12 October 2015      Published:  05 April 2016
PACS:  85.30.De (Semiconductor-device characterization, design, and modeling)  
  85.30.Tv (Field effect devices)  
  85.30.Mn (Junction breakdown and tunneling devices (including resonance tunneling devices))  
Fund: Project supported by the National Natural Science Foundation of China (Grant Nos. 61176069 and 61376079) and the Fundamental Research Funds for the Central Universities, China (Grant No. ZYGX2014Z006).
Corresponding Authors:  Xiao-Rong Luo     E-mail:  xrluo@uestc.edu.cn

Cite this article: 

Da Ma(马达), Xiao-Rong Luo(罗小蓉), Jie Wei(魏杰), Qiao Tan(谭桥), Kun Zhou(周坤), Jun-Feng Wu(吴俊峰) Ultra-low specific on-resistance high-voltage vertical double diffusion metal-oxide-semiconductor field-effect transistor with continuous electron accumulation layer 2016 Chin. Phys. B 25 048502

[1] Lin Z, Huang H M and Chen X B 2015 IEEE Trans. Electron Dev. 62 228
[2] Luo X R, Jiang Y H, Zhou K, Wang P, Wang X W, Wang Q, Yao G L, Zhang B and Li Z J 2012 IEEE Electron Dev. Lett. 33 1042
[3] Saito W, Omura I, Aida S, Koduki S, Izumisawa M, Yoshioka H, Okumura H, Yamaguchi M and Ogura T 2006 Proc. IEEE International Symposium on Power Semiconductor Devices and IC's (ISPSD 2006), p. 293
[4] Takahashi K, Kuribayashi H, Kawashima T, Wakimoto S, Mochizuki K and Nakazawa H 2006 Proc. IEEE International Symposium on Power Semiconductor Devices and IC's (ISPSD 2006), p. 297
[5] Onishi Y, Iwamoto S, Sato T, Nagaoka T, Ueno K and Fujihira T 2002 Proc. IEEE ISPSD, p. 241
[6] Tamaki T, Nakazawa Y, Kanai H, Abiko Y, Ikegami Y, Ishikawa M, Wakimoto E, Yasuda T and Eguchi S 2011 Proc. IEEE ISPSD, p. 308
[7] Luo X R, Cai J Y, Fan Y, Fan Y H, Wang X W, Wei J, Jang Y H, Zhou K, Yin C, Zhang B, Li Z J and Hu G Y 2013 IEEE Trans. Electron Dev. 60 2840
[8] Wang C L and Sun J 2009 Chin. Phys. B 18 1231
[9] Syau T, Venkatraman P and Baliga B J 1992 Electron. Lett. 28 865
[10] Li J H and Li P
[2012] CN Patent 102779836B
[11] Wang Y, Hu H F, Jiao W L and Cheng C 2010 IEEE Electron Dev. Lett. 31 338
[12] Kobayashi K, Nishiguchi T, Katoh S, Kawano T and Kawaguchi Y 2015 IEEE 27th International Symposium on Power Semiconductor Devices & IC's (ISPSD 2015), p. 141
[13] Gan K P, Liang Y C, Samudra G S, Xu S M and Yong L 2001 IEEE PESC, p. 2156
[14] Bartolf H, Mihaila A, Nistor I, Jurisch M, Leibold B and Zimmermann M 2013 IEEE Trans. Semicond. Manuf. 26 529
[15] Gan K P, Yang X, Liang Y C, Samudra G S and Yong L 2002 IEEE Electron Dev. Lett. 23 627
[1] Non-recessed-gate quasi-E-mode double heterojunction AlGaN/GaN high electron mobility transistor with high breakdown voltage
Mi Min-Han, Zhang Kai, Chen Xing, Zhao Sheng-Lei, Wang Chong, Zhang Jin-Cheng, Ma Xiao-Hua, Hao Yue. Chin. Phys. B, 2014, 23(7): 077304.
[2] A novel 4H-SiC lateral bipolar junction transistor structure with high voltage and high current gain
Deng Yong-Hui, Xie Gang, Wang Tao, Sheng Kuang. Chin. Phys. B, 2013, 22(9): 097201.
No Suggested Reading articles found!