Design optimization of a silicon-germanium heterojunction negative capacitance gate-all-around tunneling field effect transistor based on a simulation study

doi:10.1088/1674-1056/acaa2c

Abstract The steep sub-threshold swing of a tunneling field-effect transistor (TFET) makes it one of the best candidates for low-power nanometer devices. However, the low driving capability of TFETs prevents their application in integrated circuits. In this study, an innovative gate-all-around (GAA) TFET, which represents a negative capacitance GAA gate-to-source overlap TFET (NCGAA-SOL-TFET), is proposed to increase the driving current. The proposed NCGAA-SOL-TFET is developed based on technology computer-aided design (TCAD) simulations. The proposed structure can solve the problem of the insufficient driving capability of conventional TFETs and is suitable for sub-3-nm nodes. In addition, due to the negative capacitance effect, the surface potential of the channel can be amplified, thus enhancing the driving current. The gate-to-source overlap (SOL) technique is used for the first time in an NCGAA-TFET to increase the band-to-band tunneling rate and tunneling area at the silicon-germanium heterojunction. By optimizing the design of the proposed structure via adjusting the SOL length and the ferroelectric layer thickness, a sufficiently large on-state current of 17.20 upmu A can be achieved and the threshold voltage can be reduced to 0.31 V with a sub-threshold swing of 44.98 mV/decade. Finally, the proposed NCGAA-SOL-TFET can overcome the Boltzmann limit-related problem, achieving a driving current that is comparable to that of the traditional complementary metal-oxide semiconductor devices.

Keywords: negative capacitance (NC) gate-all-around (GAA) silicon-germanium heterojunction gate-to-source overlap (SOL)

Received: 21 September 2022
Revised: 16 November 2022
Accepted manuscript online: 09 December 2022

PACS:	73.40.Jn	(Metal-to-metal contacts)
	73.40.Kp	(III-V semiconductor-to-semiconductor contacts, p-n junctions, and heterojunctions)
	77.55.-g	(Dielectric thin films)
	85.35.-p	(Nanoelectronic devices)

Fund: The research presented in this work was supported by the Zhejiang Provincial Natural Science Foundation of China (Grant No. LY22F040001), the National Natural Science Foundation of China (Grant No. 62071160), and the Graduate Scientific Research Foundation of Hangzhou Dianzi University.

Corresponding Authors: Weifeng Lü
E-mail: lvwf@hdu.edu.cnn

Cite this article:

Weijie Wei(魏伟杰), Weifeng Lü(吕伟锋), Ying Han(韩颖), Caiyun Zhang(张彩云), and Dengke Chen(谌登科) Design optimization of a silicon-germanium heterojunction negative capacitance gate-all-around tunneling field effect transistor based on a simulation study 2023 Chin. Phys. B 32 097301

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Design optimization of a silicon-germanium heterojunction negative capacitance gate-all-around tunneling field effect transistor based on a simulation study

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