Surface potential-based analytical model for InGaZnO thin-film transistors with independent dual-gates

doi:10.1088/1674-1056/ab75d2

Abstract An analytical drain current model on the basis of the surface potential is proposed for indium-gallium zinc oxide (InGaZnO) thin-film transistors (TFTs) with an independent dual-gate (IDG) structure. For a unified expression of carriers' distribution for the sub-threshold region and the conduction region, the concept of equivalent flat-band voltage and the Lambert W function are introduced to solve the Poisson equation, and to derive the potential distribution of the active layer. In addition, the regional integration approach is used to develop a compact analytical current-voltage model. Although only two fitting parameters are required, a good agreement is obtained between the calculated results by the proposed model and the simulation results by TCAD. The proposed current-voltage model is then implemented by using Verilog-A for SPICE simulations of a dual-gate InGaZnO TFT integrated inverter circuit.

Keywords: analytical model independent dual-gate indium-gallium zinc oxide (InGaZnO) surface potential

Received: 18 December 2019
Revised: 29 January 2020
Accepted manuscript online:

PACS:	71.23.An	(Theories and models; localized states)
	73.43.Cd	(Theory and modeling)
	73.20.At	(Surface states, band structure, electron density of states)

Fund: Project supported by the National Key Research and Development Program of China (Grant No. 2017YFA0204600) and the Fundamental Research Funds for the Central Universities of Central South University, China (Grant No. 2019zzts424).

Corresponding Authors: Lian-Wen Deng
E-mail: denglw@csu.edu.cn

Cite this article:

Yi-Ni He(何伊妮), Lian-Wen Deng(邓联文), Ting Qin(覃婷), Cong-Wei Liao(廖聪维), Heng Luo(罗衡), Sheng-Xiang Huang(黄生祥) Surface potential-based analytical model for InGaZnO thin-film transistors with independent dual-gates 2020 Chin. Phys. B 29 047102

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Surface potential-based analytical model for InGaZnO thin-film transistors with independent dual-gates

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