A threshold voltage model for high-k gate-dielectric MOSFETs considering fringing-field effect
Ji Feng (季峰)a), Xu Jing-Ping(徐静平)a)†, and Lai Pui-To (黎沛涛)b)
a Department of Electronic Science & Technology, Huazhong University of Science and Technology, Wuhan 430074, China; b Department of Electrical & Electronic Engineering, the University of Hong Kong, Pokfulam Road, Hong Kong, China
Abstract In this paper, a threshold voltage model for high-$k$ gate-dielectric metal--oxide--semiconductor field-effect transistors (MOSFETs) is developed, with more accurate boundary conditions of the gate dielectric derived through a conformal mapping transformation method to consider the fringing-field effects including the influences of high-$k$ gate-dielectric and sidewall spacer. Comparing with similar models, the proposed model can be applied to general situations where the gate dielectric and sidewall spacer can have different dielectric constants. The influences of sidewall spacer and high-$k$ gate dielectric on fringing field distribution of the gate dielectric and thus threshold voltage behaviours of a MOSFET are discussed in detail.
Received: 06 November 2006
Revised: 08 January 2007
Accepted manuscript online:
Fund: Project supported by the National
Natural Science Foundation of China (Grant No 60376019).
Cite this article:
Ji Feng (季峰), Xu Jing-Ping(徐静平), and Lai Pui-To (黎沛涛) A threshold voltage model for high-k gate-dielectric MOSFETs considering fringing-field effect 2007 Chinese Physics 16 1757
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