Please wait a minute...
Chin. Phys. B, 2023, Vol. 32(6): 068501    DOI: 10.1088/1674-1056/acbe32
INTERDISCIPLINARY PHYSICS AND RELATED AREAS OF SCIENCE AND TECHNOLOGY Prev   Next  

A non-quasi-static model for nanowire gate-all-around tunneling field-effect transistors

Bin Lu(芦宾)1, Xin Ma(马鑫)1, Dawei Wang(王大为)1, Guoqiang Chai(柴国强)1, Linpeng Dong(董林鹏)2, and Yuanhao Miao(苗渊浩)3,†
1 School of Physics and Information Engineering, Shanxi Normal University, Taiyuan 030000, China;
2 Shaanxi Province Key Laboratory of Thin Films Technology&Optical Test, Xi'an Technological University, Xi'an 710032, China;
3 Research and Development Center of Optoelectronic Hybrid IC, Guangdong Greater Bay Area Institute of Integrated Circuit and System, Guangzhou 510535, China
Abstract  Nanowires with gate-all-around (GAA) structures are widely considered as the most promising candidate for 3-nm technology with the best ability of suppressing the short channel effects, and tunneling field effect transistors (TFETs) based on GAA structures also present improved performance. In this paper, a non-quasi-static (NQS) device model is developed for nanowire GAA TFETs. The model can predict the transient current and capacitance varying with operation frequency, which is beyond the ability of the quasi-static (QS) model published before. Excellent agreements between the model results and numerical simulations are obtained. Moreover, the NQS model is derived from the published QS model including the current-voltage (I-V) and capacitance-voltage (C-V) characteristics. Therefore, the NQS model is compatible with the QS model for giving comprehensive understanding of GAA TFETs and would be helpful for further study of TFET circuits based on nanowire GAA structure.
Keywords:  tunneling field effect transistor      relaxation time approximation      non-quasi-static      non-quasi-static  
Received:  13 November 2022      Revised:  06 January 2023      Accepted manuscript online:  23 February 2023
PACS:  85.30.Tv (Field effect devices)  
  85.35.-p (Nanoelectronic devices)  
  73.40.Qv (Metal-insulator-semiconductor structures (including semiconductor-to-insulator))  
  61.82.Fk (Semiconductors)  
Fund: Project supported by the National Natural Science Foundation of China (Grant Nos. 62004119 and 62201332), and the Applied Basic Research Plan of Shanxi Province, China (Grant Nos. 20210302124647 and 20210302124028).
Corresponding Authors:  Yuanhao Miao     E-mail:  miaoyuanhao@giics.com.cn

Cite this article: 

Bin Lu(芦宾), Xin Ma(马鑫), Dawei Wang(王大为), Guoqiang Chai(柴国强),Linpeng Dong(董林鹏), and Yuanhao Miao(苗渊浩) A non-quasi-static model for nanowire gate-all-around tunneling field-effect transistors 2023 Chin. Phys. B 32 068501

[1] Cheng W J, Liang R R, Xu G B, Yu G F, Zhang S Q, Yin H X, Zhao C, Ren T L and Xu J2020 IEEE J. Electron Device Soc. 8 336
[2] Lu B, Cui Y, Guo A X, Wang D W, Lv Z J, Zhou J R and Miao Y H2021 IEEE Trans. Electron Devices 68 1537
[3] Li W C and Jason C S W2020 IEEE Trans. Electron Devices 67 1480
[4] Lu B, Lu H L, Zhang Y M, Zhang Y M, Cui X R, Lv Z J and Liu C2018 IEEE Trans. Electron Devices 65 3555
[5] Shao Q M, Zhao C, Wu C, Zhang J Y, Zhang L and Yu Z P2013 IEEE International Conference of Electron Devices and Solid-state Circuits, June 3-5, 2013, Hong Kong, China, p. 1
[6] Verhulst A S, Sorée B, Leonelli D, Vandenberghe W G and Groeseneken G2010 J. Appl. Phys. 107 24518
[7] Luisier M and Klimeck G2009 IEEE Electron Device Lett. 30 602
[8] Radamson H H, Zhu H L, Wu Z H, He X B, Lin H X, Liu J B, Xiang J J, Kong Z Z, Xiong W J, Li J J, Gui H S, Gao J F, Yang H, Du Y, Xu B Q, Li B, Zhao X W, Yu J H, Dong Y and Wang G L2020 Nanomaterials 10 1555
[9] Narang R, Saxena M and Gupta M2019 IEEE Sensors J. 19 2605
[10] Bagga N and Dasgupta S2017 IEEE Trans. Electron Devices 64 606
[11] Vishnoi R and Kumar M J2015 IEEE Trans. Nanotechnol. 14 358
[12] Vishnoi R and Kumar M J2014 IEEE Trans. Electron Devices 61 2599
[13] Kumar S, Goel E, Singh K, Singh B, Kumar M and Jit S2016 IEEE Trans. Electron Devices 63 3291
[14] Kumar S, Goel E, Singh K, Singh B, Singh P K, Baral K and Jit S2017 IEEE Trans. Electron Devices 64 960
[15] Singh P K, Baral K, Kumar S, Tripathy M R, Singh A K, Upadhyay R K, Chander S and Jit S2021 Silicon 13 1731
[16] Zhang L, He J and Chan M2012 International Electron Devices Meeting, December 10-13, 2012, San Francisco, USA, p. 6.8.1
[17] Zhang L and Chan M2014 IEEE Trans. Electron Devices 61 300
[18] Keighobadi D, Mohammadi S and Fathipour M2019 IEEE Trans. Electron Devices 66 3646
[19] Guan Y, Li Z, Zhang W, Zhang Y and Liang F2018 IEEE Trans. Electron Devices 65 776
[20] Khaveh H R T and Mohammadi S2016 IEEE Trans. Electron Devices 63 5021
[21] Lin Y, Khandelwal S, Duarte J P, Chang H, Salahuddin S and Hu C2017 IEEE Trans. Electron Devices 64 599
[22] Kumar S, Singh K, Chander S, Goel E, Singh P K, Baral K, Singh B and Jit S2018 IEEE Trans. Electron Devices 65 331
[23] Lu B, Wang D W, Cui Y, Li Z, Chai G Q, Dong L P, Zhou J R, Wang G L, Miao Y H, Lv Z J and Lu H L2021 IEEE Trans. Electron Devices 69 419
[24] Cho S, Lee J S, Kim K R, Park B G, Harris J S, Jr and Kang I M2011 IEEE Trans. Electron Devices 58 4164
[25] Chan M, Hui K Y, Hu C M and Ko P K1998 IEEE Trans. Electron Devices 45 834
[26] Park H J, Hui K Y, Ko P K and Hu C M1992 IEEE Trans. Comput.-Aided Des. 11 1247
[27] Smedes T and Klaassen F M1995 Solid-State Electron. 38 121
[28] Sallese J M and Porret A S2000 Solid-State Electron. 44 887
[29] Porret A S, Sallese J M and Enz C C2001 IEEE Trans. Electron Devices 48 1647
[30] Roy A S, Enz C C and Sallese J M2006 IEEE Trans. Electron Devices 53 2044
[31] Scholten A J, Tiemeijer L F, Vreede P W H and Klaassen D B M1999 International Electron Devices Meeting, December 5-8, 1999, Washington, USA, p. 163
[32] Wang H, Chen T L and Gildenblat G2003 IEEE Trans. Electron Devices 50 2262
[33] Navarro D, Takeda Y, Miyake M, Nakayama N, Machida K, Ezaki T, Mattausch H J and Mattausch M2006 IEEE Trans. Electron Devices 53 2025
[34] Chai K W and Paulos J J1989 IEEE Trans. Electron Devices 36 2513
[35] Stiebler W C2006 European Microwave Integrated Circuits Conference, September 10-13, 2006, Manchester, UK, p. 387
[36] Lu B, Lv Z J, Lu H L and Cui Y2019 IEEE Electron Device Lett. 40 1996
[37] Zhu Z, Gildenblat G and McAndrew C C2012 IEEE Trans. Electron Devices 59 1236
[38] Devi W V, Bhowmick B and Pukhrambam P D2020 IEEE Trans. Electron Devices 67 2133
[39] Dutta R, Subash T D and Paitya N2021 Silicon 13 1453
[40] Synopsys 2010 TCAD Sentaurus Device User's Manual (Mountain View, CA, USA)
[41] Dasgupta A, Rastogi P, Agarwal A, Hu C and Chauhan Y S2018 IEEE Trans. Electron Devices 65 1094
[42] Verhulst A S, Sorée B, Leonelli D, Vandenberghe W G and Groeseneken G2010 J. Appl. Phys. 107 24518
[43] Singh P K, Baral K, Kumar S, Tripathy M R, Singh A K, Upadhyay R K, Chander S and Jit S2021 Silicon 13 1731
[44] Ma N and Jena D2013 Appl. Phys. Lett. 102 132102
[45] Pan A and Chui C O2014 J. Appl. Phys. 116 054509
[46] Lu B, Lu H L, Zhang Y M, Zhang Y M, Cui X R, Lv Z J, Yang S Z and Liu C2017 IEEE Trans. Electron Devices 65 299
[47] Katsuhiro T, Masatoshi Y and Takashi F2012 Symposium on VLSI Technology (VLSIT), June 12-14, 2012, Honolulu, USA
[48] Shao Y and Del A J A2022 IEEE Electron Device Lett. 43 846
[49] Moselund K E, Cutaia D, Schmid H, Brog M, Sant S, Schenk A and Riel H2016 IEEE Trans. Electron Devices 63 4233
[50] Richter S, Trellenkamp S, Schäfer A, Hartmann J M, Bourdelle K K, Zhao Q T and Mantl S2015 Solid-State Electron. 108 97
[51] Hellenbrand M, Memisevic E, Svensson J, Krishnaraja A, Lind E and Wernersson L E2018 IEEE Electron Device Lett. 39 943
[52] Krishnaraja A, Svensson J, Memisevic ES, Zhu Z, Persson A, Lind E, Wallenberg L and Wernersson L2020 ACS Appl. Electron. Mater. 2 2882
[53] Cutaia D, Moselund K E, Borg M, Heinz S, Lynne G, Chris M B, Siegfried K, Emanuele U and Heike R2015 IEEE J. Electron Devices Soc. 3 176
[1] Optimization of ambipolar current and analog/RF performance for T-shaped tunnel field-effect transistor with gate dielectric spacer
Ru Han(韩茹), Hai-Chao Zhang(张海潮), Dang-Hui Wang(王党辉), Cui Li(李翠). Chin. Phys. B, 2019, 28(1): 018505.
[2] Tunneling field effect transistors based on in-plane and vertical layered phosphorus heterostructures
Shenyan Feng(冯申艳), Qiaoxuan Zhang(张巧璇), Jie Yang(杨洁), Ming Lei(雷鸣), Ruge Quhe(屈贺如歌). Chin. Phys. B, 2017, 26(9): 097401.
[3] An analytic model for gate-all-around silicon nanowire tunneling field effect transistors
Liu Ying (刘颖), He Jin (何进), Chan Mansun (陈文新), Du Cai-Xia (杜彩霞), Ye Yun (叶韵), Zhao Wei (赵巍), Wu Wen (吴文), Deng Wan-Ling (邓婉玲), Wang Wen-Ping (王文平). Chin. Phys. B, 2014, 23(9): 097102.
No Suggested Reading articles found!