Please wait a minute...
Chin. Phys. B, 2019, Vol. 28(1): 018505    DOI: 10.1088/1674-1056/28/1/018505
INTERDISCIPLINARY PHYSICS AND RELATED AREAS OF SCIENCE AND TECHNOLOGY Prev   Next  

Optimization of ambipolar current and analog/RF performance for T-shaped tunnel field-effect transistor with gate dielectric spacer

Ru Han(韩茹), Hai-Chao Zhang(张海潮), Dang-Hui Wang(王党辉), Cui Li(李翠)
School of Computer Science and Engineering, Northwestern Polytechnical University, Xi'an 710072, China
Abstract  

A new T-shaped tunnel field-effect transistor (TTFET) with gate dielectric spacer (GDS) structure is proposed in this paper. To further studied the effects of GDS structure on the TTFET, detailed device characteristics such as current-voltage relationships, energy band diagrams, band-to-band tunneling (BTBT) rate and the magnitude of the electric field are investigated by using TCAD simulation. It is found that compared with conventional TTFET and TTFET with gate-drain overlap (GDO) structure, GDS-TTFET not only has the minimum ambipolar current but also can suppress the ambipolar current under a more extensive bias range. Furthermore, the analog/RF performances of GDS-TTFET are also investigated in terms of transconductance, gate-source capacitance, gate-drain capacitance, cutoff frequency, and gain bandwidth production. By inserting a low-κ spacer layer between the gate electrode and the gate dielectric, the GDS structure can effectively reduce parasitic capacitances between the gate and the source/drain, which leads to better performance in term of cutoff frequency and gain bandwidth production. Finally, the thickness of the gate dielectric spacer is optimized for better ambipolar current suppression and improved analog/RF performance.

Keywords:  tunneling field effect transistor      T-shaped tunnel field-effect transistor      gate dielectric spacer      ambipolar current      analog/RF performance  
Received:  13 August 2018      Revised:  28 September 2018      Accepted manuscript online: 
PACS:  85.30.De (Semiconductor-device characterization, design, and modeling)  
  85.30.Tv (Field effect devices)  
  85.30.Mn (Junction breakdown and tunneling devices (including resonance tunneling devices))  
Fund: 

Project supported by the National Natural Science Foundation of China (Grant Nos. 61306116 and 61472322).

Corresponding Authors:  Ru Han     E-mail:  hanru@nwpu.edu.cn

Cite this article: 

Ru Han(韩茹), Hai-Chao Zhang(张海潮), Dang-Hui Wang(王党辉), Cui Li(李翠) Optimization of ambipolar current and analog/RF performance for T-shaped tunnel field-effect transistor with gate dielectric spacer 2019 Chin. Phys. B 28 018505

[1] Taur Y, Buchanan D A, ChenW, Frank D J, Ismail K E, Lo S H, SaiHalasz G A, Viswanathan R G, Wann H J C, Wind S J andWong H S 1997 Proceedings of the IEEE 85 486
[2] Frank D J, Dennard R H, Nowak E, Solomon P M, Taur Y and Wong H S P 2001 Proceedings of the IEEE 89 259
[3] Colinge J P 2004 Solid-State Electronics 48 897
[4] Wang P F, Hilsenbeck K, Nirschl T, Oswald M, Stepper C, Weis M, Schmitt-Landsiedel D and Hansch W 2004 Solid-State Electronics 48 2281
[5] Frank D J 2002 IBM Journal of Research and Development 46 235
[6] Iwai H 2009 Microelectronic Engineering 86 1520
[7] Zhang Q, Zhao W and Seabaugh A 2006 IEEE Electron Device Letters 27 297
[8] Choi W Y, Park B G, Lee J D and Liu T J K 2007 IEEE Electron Device Letters 28 743
[9] Boucart K and Ionescu A M 2007 IEEE Transactions on Electron Devices 54 1725
[10] Mayer F, Royer C L, Damlencourt J F, Romanjek K, Andrieu F, Tabone C, Previtali B and Deleonibus S 2008 IEEE International Electron Devices Meeting 2008 1
[11] Verhulst A S, Vandenberghe W G, Maex K and Groeseneken G 2008 J. Appl. Phys. 104 064514
[12] Seabaugh A C and Zhang Q 2010 Proceedings of the IEEE 98 2095
[13] Ionescu A M and Riel H 2011 Nature 479 329
[14] Guan Y H, Li Z C, Luo D X, Meng Q Z and Zhang Y F 2016 Chin. Phys. B 25 108502
[15] Kang H Y, Hu H Y and Wang B 2016 Chin. Phys. B 25 118501
[16] Toh E H, Wang G H, Chan L, Samudra G and Yeo Y C 2007 Appl. Phys. Lett. 91 243505
[17] Kao K H, Verhulst A S, Vandenberghe W G, Soree B, Groeseneken G and De Meyer K 2012 IEEE Transactions on Electron Devices 59 292
[18] Vandooren A, Leonelli D, Rooyackers R, Arstila K, Groeseneken G and Huyghebaert C 2012 Solid-State Electronics 72 82
[19] Raad B, Nigam K, Sharma D and Kondekar P 2016 Electronics Letters 52 770
[20] Jiang Z, Zhuang Y Q, Li C, Wang P and Liu Y Q 2016 Chinese Physics B 25 027701
[21] Feng S, Zhang Q, Yang J, Lei M and Quhe R 2017 Chin. Phys. B 26 097401
[22] Low K L, Zhan C, Han G, Yang Y, Goh K H, Guo P, Toh E H and Yeo Y C 2012 Jpn J. Appl. Phys. 51 02BC04
[23] Kim S W, Choi W Y, Sun M C, Kim H W and Park B G 2012 Jpn J. Appl. Phys. 51 06FE09
[24] Kim J H, Kim S W, Kim H W and Park B G 2015 Electronics Letters 51 718
[25] Yang Z 2016 IEEE Electron Device Letters 37 839
[26] Li W, Liu H, Wang S and Chen S 2016 Superlattices and Microstructures 100 1238
[27] Li W, Liu H, Wang S, Chen S and Yang Z 2017 Nanoscale Research Letters 12 198
[28] Imenabadi R M, Saremi M and Vandenberghe W G 2017 IEEE Transactions on Electron Devices 64 4752
[29] Yang Z, Zhang Y, Yang Y and Yu N 2017 Superlattices and Microstructures 111 1226
[30] Zhang W H, Li Z C, Guan Y H and Zhang Y F 2017 Chin. Phys. B 26 018504
[31] Li C, Yan Z R, Zhuang Y Q, Zhao X L and Guo J M 2018 Chin. Phys. B 27 078502
[32] Li C, Zhao X, Zhuang Y, Yan Z, Guo J and Han R 2018 Superlattices and Microstructures 115 154
[33] Kim S W, Kim J H, Liu T J K, Choi W Y and Park B G 2016 IEEE Transactions on Electron Devices 63 1774
[34] Dubey P K and Kaushik B K 2017 IEEE Transactions on Electron Devices 64 3120
[35] Ding L, Gnani E, Gerardin S, Bagatin M, Driussi F, Palestri P, Selmi L, Royer C L and Paccagnella A 2015 IEEE Transactions on Device and Materials Reliability 15 236
[36] Ghosh S, Koley K and Sarkar C K 2015 Microelectronics Reliability 55 326
[37] Kwon D W, Kim H W, Kim J H, Park E, Lee J, Kim W, Kim S, Lee J H and Park B G 2017 IEEE Transactions on Electron Devices 64 1799
[1] Analysis of non-uniform hetero-gate-dielectric dual-material control gate TFET for suppressing ambipolar nature and improving radio-frequency performance
Hui-Fang Xu(许会芳), Jian Cui(崔健), Wen Sun(孙雯), Xin-Feng Han(韩新风). Chin. Phys. B, 2019, 28(10): 108501.
[2] Tunneling field effect transistors based on in-plane and vertical layered phosphorus heterostructures
Shenyan Feng(冯申艳), Qiaoxuan Zhang(张巧璇), Jie Yang(杨洁), Ming Lei(雷鸣), Ruge Quhe(屈贺如歌). Chin. Phys. B, 2017, 26(9): 097401.
[3] An analytic model for gate-all-around silicon nanowire tunneling field effect transistors
Liu Ying (刘颖), He Jin (何进), Chan Mansun (陈文新), Du Cai-Xia (杜彩霞), Ye Yun (叶韵), Zhao Wei (赵巍), Wu Wen (吴文), Deng Wan-Ling (邓婉玲), Wang Wen-Ping (王文平). Chin. Phys. B, 2014, 23(9): 097102.
No Suggested Reading articles found!