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Chin. Phys. B, 2020, Vol. 29(10): 107401    DOI: 10.1088/1674-1056/ab99b5

Simulation study of device physics and design of GeOI TFET with PNN structure and buried layer for high performance

Bin Wang(王斌)1,†, Sheng Hu(胡晟)1, Yue Feng(冯越)1, Peng Li(李鹏)2, Hui-Yong Hu(胡辉勇)1, and Bin Shu(舒斌)1
1 State Key Discipline Laboratory of Wide Bandgap Semiconductor Technology, School of Microelectronics, Xidian University, Xi’an 710071, China
2 Xi’an Microelectronic Technology Institute, Xi’an 710054, China

Large threshold voltage and small on-state current are the main limitations of the normal tunneling field effect transistor (TFET). In this paper, a novel TFET with gate-controlled P+N+N+ structure based on partially depleted GeOI (PD-GeOI) substrate is proposed. With the buried P+-doped layer (BP layer) introduced under P+N+N+ structure, the proposed device behaves as a two-tunneling line device and can be shut off by the BP junction, resulting in a high on-state current and low threshold voltage. Simulation results show that the on-state current density Ion of the proposed TFET can be as large as 3.4 × 10−4 A/μm, and the average subthreshold swing (SS) is 55 mV/decade. Moreover, both of Ion and SS can be optimized by lengthening channel and buried P+ layer. The off-state current density of TTP TFET is 4.4 × 10−10 A/μm, and the threshold voltage is 0.13 V, showing better performance than normal germanium-based TFET. Furthermore, the physics and device design of this novel structure are explored in detail.

Keywords:  Ge-based TFET      two line tunneling paths      point tunneling      on-state current density  
Received:  23 April 2020      Revised:  26 May 2020      Accepted manuscript online:  05 June 2020
PACS:  74.55.+v (Tunneling phenomena: single particle tunneling and STM)  
  85.30.Tv (Field effect devices)  
  85.30.De (Semiconductor-device characterization, design, and modeling)  
Corresponding Authors:  Corresponding author. E-mail:   
About author: 
†Corresponding author. E-mail:
* Project supported by the National Natural Science Foundation of China (Grant No. 61704130), the Science Research Plan in Shaanxi Province, China (Grant No. 2018JQ6064), and the Science and Technology Project on Analog Integrated Circuit Laboratory, China (Grant No. JCKY2019210C029).

Cite this article: 

Bin Wang(王斌)†, Sheng Hu(胡晟), Yue Feng(冯越), Peng Li(李鹏), Hui-Yong Hu(胡辉勇), and Bin Shu(舒斌) Simulation study of device physics and design of GeOI TFET with PNN structure and buried layer for high performance 2020 Chin. Phys. B 29 107401

Fig. 1.  

Cross section of device structure of normal PNN TFET based on FD-GeOI.

Fig. 2.  

Cross-section of two tunneling paths (TTP) TFET based on PD-GeOI substrate.

Fig. 3.  

Computed energy-band diagrams of TTP TFET for both off-state (solid line, |VDS| = 1 V, VGS = 0 V) and on-state (dashed line, |VDS| = 1 V, VGS = 1 V) along (a) line tunneling path 1 and (b) line tunneling path 2.

Gate length Lch/nm 100 100
Channel doping/cm−3 1 × 1019 1 × 1019
HfO2 thickness Tox/nm 3 3
Buried layer length LBP/nm 50
Epitaxial layer doping Nepicm−3 1 × 1017
Buried doing NBP/cm−3 1 × 1020
Lightly doped region NLD/cm−3 5 × 1018
Gate metal aluminum gold
Source/drain-metal aluminum aluminum
Source/drain-doping/cm−3 1 × 1020 1 × 1020
Table 1.  

Simulated device parameters used in this study.

Fig. 4.  

Transfer characteristics of FD-GOI TFET and proposed TTP TFET.

Fig. 5.  

Composition of current of the proposed TTP TFET.

Fig. 6.  

Transfer characteristics of TTP TFET for different lengths of buried layer LBP.

Fig. 7.  

Distributions of surface electron density along x axis of TTP TFET for different values of LBP at VGS = 1 V and VDS = 1 V.

Fig. 8.  

Point tunneling width when LBP = 50 nm and 100 nm at VGS = 0 V and VDS = 1 V.

Fig. 9.  

Band bending from channel to LDR along x axis at the upper right-hand corner of the buried layer for (a) off-state at VDS = 1 V, VGS = 0 V and (b) on-state at VDS = 1 V, VGS = 1 V.

Fig. 10.  

Transfer characteristics of TTP TFET for different doping concentrations of slightly doped region (NLDR).

Fig. 11.  

Plots of optimized performance of TTP TFET for LBP = 50 nm, 250 nm, 450 nm, and 650 nm at Lgap = 50 nm.

Fig. 12.  

Output characteristics of TTP TFET.

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