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A novel P-channel SOI LDMOS structure with non-depletion potential-clamped layer |
| Wei Li(李威)1, Zhi Zheng(郑直)2, Zhigang Wang(汪志刚)3, Ping Li(李平)1, Xiaojun Fu(付晓君)2, Zhengrong He(何峥嵘)2, Fan Liu(刘凡)2, Feng Yang(杨丰)2, Fan Xiang(向凡)2, Luncai Liu(刘伦才)2 |
1. State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu 610054, China;
2. National Laboratory of Analog ICs, Sichuan Institute of Solid-State Circuits, CETC, Chongqing 400060, China;
3. School of Information Science and Technology, Southwest Jiaotong University, Chengdu 611756, China |
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Abstract A novel structure is proposed for doubling the vertical breakdown voltage of silicon-on-insulator (SOI) devices. In this new structure, the conventional buried oxide (BOX) in an SOI device is split into two sections:the source-section BOX and the drain-section BOX. A highly-doped Si layer, referred to as a non-depletion potential-clamped layer (NPCL), is positioned under and close to the two BOX sections. In the split BOXes and the Si region above the BOXes, the blocking voltage (BV) is divided into two parts by the NPCL. The voltage in the NPCL is clamped to be nearly half of the drain voltage. When the drain voltage approaches a breakdown value, the voltage sustained by the source-section BOX and the Si region under the source are nearly the same as the voltage sustained by the drain-section BOX and the Si region under the drain. The vertical BV is therefore almost doubled. The effectiveness of this new structure was verified for a P-channel SOI lateral double-diffused metal-oxide semiconductor (LDMOS) and can be applied to other high-voltage SOI devices. The simulation results show that the BV in an NPCL P-channel SOI LDMOS is improved by 55% and the specific on-resistance (Ron,sp) is reduced by 69% in comparison to the conventional structure.
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Received: 31 May 2016
Revised: 24 September 2016
Accepted manuscript online:
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PACS:
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77.55.df
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(For silicon electronics)
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85.30.De
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(Semiconductor-device characterization, design, and modeling)
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51.50.+v
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(Electrical properties)
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| Fund: Project supported by the National Natural Science Foundation of China (Grant No. 61404110) and the National Higher-Education Institution General Research and Development Project, China (Grant No. 2682014CX097). |
Corresponding Authors:
Zhi Zheng
E-mail: zhizh734@gmail.com
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Cite this article:
Wei Li(李威), Zhi Zheng(郑直), Zhigang Wang(汪志刚), Ping Li(李平), Xiaojun Fu(付晓君), Zhengrong He(何峥嵘), Fan Liu(刘凡), Feng Yang(杨丰), Fan Xiang(向凡), Luncai Liu(刘伦才) A novel P-channel SOI LDMOS structure with non-depletion potential-clamped layer 2017 Chin. Phys. B 26 017701
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