Partial-SOI high voltage P-channel LDMOS with interface accumulation holes

doi:10.1088/1674-1056/20/10/107101

中国物理B ›› 2011, Vol. 20 ›› Issue (10): 107101-107101.doi: 10.1088/1674-1056/20/10/107101

Partial-SOI high voltage P-channel LDMOS with interface accumulation holes

胡盛东¹, 罗小蓉², 张波², 李肇基², 吴丽娟³

(1)College of Communication Engineering, Chongqing University, Chongqing 400044, China; (2)State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu 610054, China; (3)State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu 610054, China; College of Communication Engineering, Chengdu University of Information Technology, Chengdu 610225, Chin

收稿日期:2010-11-02 修回日期:2011-02-21 出版日期:2011-10-15 发布日期:2011-10-15
基金资助:
Project supported by the National Natural Science Foundation of China (Grant Nos. 60806025 and 60976060), the Funds of the National Laboratory of Analog Integrated Circuit (Grant No. 9140C0903070904), and the Youth Teacher Foundation of the University of Electronic Science and Technology of China (Grant No. jx0721).

Partial-SOI high voltage P-channel LDMOS with interface accumulation holes

Wu Li-Juan(吴丽娟)^a)b)†, Hu Sheng-Dong(胡盛东)^c), Luo Xiao-Rong(罗小蓉)^a), Zhang Bo(张波)^a), and Li Zhao-Ji(李肇基)^a)

^a State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu 610054, China; ^b College of Communication Engineering, Chengdu University of Information Technology, Chengdu 610225, China; ^c College of Communication Engineering, Chongqing University, Chongqing 400044, China

Received:2010-11-02 Revised:2011-02-21 Online:2011-10-15 Published:2011-10-15
Supported by:
Project supported by the National Natural Science Foundation of China (Grant Nos. 60806025 and 60976060), the Funds of the National Laboratory of Analog Integrated Circuit (Grant No. 9140C0903070904), and the Youth Teacher Foundation of the University of Electronic Science and Technology of China (Grant No. jx0721).

摘要/Abstract

摘要： A new partial SOI (silion-on-insulator) (PSOI) high voltage P-channel LDMOS (lateral double-diffused metal-oxide semiconductor) with an interface hole islands (HI) layer is proposed and its breakdown characteristics are investigated theoretically. A high concentration of charges accumulate on the interface, whose density changes with the negative drain voltage, which increase the electric field (E_I) in the dielectric buried oxide layer (BOX) and modulate the electric field in drift region . This results in the enhancement of the breakdown voltage (BV). The values of E_I and BV of an HI PSOI with a 2-μm thick SOI layer over a 1-μm thick buried layer are 580V/μm and -582 V, respectively, compared with 81.5 V/μm and -123 V of a conventional PSOI. Furthermore, the Si window also alleviates the self-heating effect (SHE). Moreover, in comparison with the conventional device, the proposed device exhibits low on-resistance.

关键词: interface charges, breakdown voltage, partial-SOI, accumulation holes, self-heating effect

Abstract: A new partial SOI (silion-on-insulator) (PSOI) high voltage P-channel LDMOS (lateral double-diffused metal-oxide semiconductor) with an interface hole islands (HI) layer is proposed and its breakdown characteristics are investigated theoretically. A high concentration of charges accumulate on the interface, whose density changes with the negative drain voltage, which increase the electric field (E_I) in the dielectric buried oxide layer (BOX) and modulate the electric field in drift region . This results in the enhancement of the breakdown voltage (BV). The values of E_I and BV of an HI PSOI with a 2-μm thick SOI layer over a 1-μm thick buried layer are 580V/μm and -582 V, respectively, compared with 81.5 V/μm and -123 V of a conventional PSOI. Furthermore, the Si window also alleviates the self-heating effect (SHE). Moreover, in comparison with the conventional device, the proposed device exhibits low on-resistance.

Key words: interface charges, breakdown voltage, partial-SOI, accumulation holes, self-heating effect

中图分类号: (Theories and models of many-electron systems)

71.10.-w

73.20.-r (Electron states at surfaces and interfaces) 73.40.Qv (Metal-insulator-semiconductor structures (including semiconductor-to-insulator))

吴丽娟, 胡盛东, 罗小蓉, 张波, 李肇基. Partial-SOI high voltage P-channel LDMOS with interface accumulation holes[J]. 中国物理B, 2011, 20(10): 107101-107101.

Wu Li-Juan(吴丽娟), Hu Sheng-Dong(胡盛东), Luo Xiao-Rong(罗小蓉), Zhang Bo(张波), and Li Zhao-Ji(李肇基). Partial-SOI high voltage P-channel LDMOS with interface accumulation holes[J]. Chin. Phys. B, 2011, 20(10): 107101-107101.

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Partial-SOI high voltage P-channel LDMOS with interface accumulation holes

Partial-SOI high voltage P-channel LDMOS with interface accumulation holes

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