Numerical and analytical investigations for the SOI LDMOS with alternated high-k dielectric and step doped silicon pillars

doi:10.1088/1674-1056/ab6960

中国物理B ›› 2020, Vol. 29 ›› Issue (3): 38503-038503.doi: 10.1088/1674-1056/ab6960

• INTERDISCIPLINARY PHYSICS AND RELATED AREAS OF SCIENCE AND TECHNOLOGY • 上一篇下一篇

Numerical and analytical investigations for the SOI LDMOS with alternated high-k dielectric and step doped silicon pillars

Jia-Fei Yao(姚佳飞), Yu-Feng Guo(郭宇锋), Zhen-Yu Zhang(张振宇), Ke-Meng Yang(杨可萌), Mao-Lin Zhang(张茂林), Tian Xia(夏天)

1 College of Electronic and Optical Engineering&College of Microelectronics, Nanjing University of Posts and Telecommunications, Nanjing 210023, China;
2 National and Local Joint Engineering Laboratory of RF Integration and Micro-Assembly Technology, Nanjing 210023, China;
3 School of Electrical Engineering, University of Vermont, Burlington, VT 05405, USA

收稿日期:2019-10-17 修回日期:2019-12-16 出版日期:2020-03-05 发布日期:2020-03-05
通讯作者: Yu-Feng Guo E-mail:yfguo@njupt.edu.cn
基金资助:
Project supported by the National Natural Science Foundation of China (Grant Nos. 61704084 and 61874059).

Numerical and analytical investigations for the SOI LDMOS with alternated high-k dielectric and step doped silicon pillars

Jia-Fei Yao(姚佳飞)^1,2, Yu-Feng Guo(郭宇锋)^1,2, Zhen-Yu Zhang(张振宇)^1,2, Ke-Meng Yang(杨可萌)^1,2, Mao-Lin Zhang(张茂林)^1,2, Tian Xia(夏天)³

1 College of Electronic and Optical Engineering&College of Microelectronics, Nanjing University of Posts and Telecommunications, Nanjing 210023, China;
2 National and Local Joint Engineering Laboratory of RF Integration and Micro-Assembly Technology, Nanjing 210023, China;
3 School of Electrical Engineering, University of Vermont, Burlington, VT 05405, USA

Received:2019-10-17 Revised:2019-12-16 Online:2020-03-05 Published:2020-03-05
Contact: Yu-Feng Guo E-mail:yfguo@njupt.edu.cn
Supported by:
Project supported by the National Natural Science Foundation of China (Grant Nos. 61704084 and 61874059).

摘要/Abstract

摘要： This paper presents a new silicon-on-insulator (SOI) lateral-double-diffused metal-oxide-semiconductor transistor (LDMOST) device with alternated high-k dielectric and step doped silicon pillars (HKSD device). Due to the modulation of step doping technology and high-k dielectric on the electric field and doped profile of each zone, the HKSD device shows a greater performance. The analytical models of the potential, electric field, optimal breakdown voltage, and optimal doped profile are derived. The analytical results and the simulated results are basically consistent, which confirms the proposed model suitable for the HKSD device. The potential and electric field modulation mechanism are investigated based on the simulation and analytical models. Furthermore, the influence of the parameters on the breakdown voltage (BV) and specific on-resistance (R_on,sp) are obtained. The results indicate that the HKSD device has a higher BV and lower R_on,sp compared to the SD device and HK device.

关键词: high-k dielectric, step doped silicon pillar, model, breakdown voltage

Abstract: This paper presents a new silicon-on-insulator (SOI) lateral-double-diffused metal-oxide-semiconductor transistor (LDMOST) device with alternated high-k dielectric and step doped silicon pillars (HKSD device). Due to the modulation of step doping technology and high-k dielectric on the electric field and doped profile of each zone, the HKSD device shows a greater performance. The analytical models of the potential, electric field, optimal breakdown voltage, and optimal doped profile are derived. The analytical results and the simulated results are basically consistent, which confirms the proposed model suitable for the HKSD device. The potential and electric field modulation mechanism are investigated based on the simulation and analytical models. Furthermore, the influence of the parameters on the breakdown voltage (BV) and specific on-resistance (R_on,sp) are obtained. The results indicate that the HKSD device has a higher BV and lower R_on,sp compared to the SD device and HK device.

Key words: high-k dielectric, step doped silicon pillar, model, breakdown voltage

中图分类号: (Semiconductor-device characterization, design, and modeling)

85.30.De

85.30.Tv (Field effect devices) 73.40.Qv (Metal-insulator-semiconductor structures (including semiconductor-to-insulator))

姚佳飞, 郭宇锋, 张振宇, 杨可萌, 张茂林, 夏天. Numerical and analytical investigations for the SOI LDMOS with alternated high-k dielectric and step doped silicon pillars[J]. 中国物理B, 2020, 29(3): 38503-038503.

Jia-Fei Yao(姚佳飞), Yu-Feng Guo(郭宇锋), Zhen-Yu Zhang(张振宇), Ke-Meng Yang(杨可萌), Mao-Lin Zhang(张茂林), Tian Xia(夏天). Numerical and analytical investigations for the SOI LDMOS with alternated high-k dielectric and step doped silicon pillars[J]. Chin. Phys. B, 2020, 29(3): 38503-038503.

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Numerical and analytical investigations for the SOI LDMOS with alternated high-k dielectric and step doped silicon pillars

Numerical and analytical investigations for the SOI LDMOS with alternated high-k dielectric and step doped silicon pillars

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