Variable-K double trenches SOI LDMOS with high-concentration P-pillar

doi:10.1088/1674-1056/ab7e94

中国物理B ›› 2020, Vol. 29 ›› Issue (5): 57701-057701.doi: 10.1088/1674-1056/ab7e94

• CONDENSED MATTER: ELECTRONIC STRUCTURE, ELECTRICAL, MAGNETIC, AND OPTICAL PROPERTIES • 上一篇下一篇

Variable-K double trenches SOI LDMOS with high-concentration P-pillar

Lijuan Wu(吴丽娟), Lin Zhu(朱琳), Xing Chen(陈星)

The Hunan Provincial Key Laboratory of Flexible Electronic Materials Genome Engineering, School of Physics&Electronic Science, Changsha University of Science&Technology, Changsha 410114, China

收稿日期:2019-11-06 修回日期:2020-03-06 出版日期:2020-05-05 发布日期:2020-05-05
通讯作者: Lijuan Wu E-mail:1329456829@qq.com
基金资助:
Project supported by the Scientific Research Fund of Hunan Provincial Education Department, China (Grant No. 19K001).

Variable-K double trenches SOI LDMOS with high-concentration P-pillar

Lijuan Wu(吴丽娟), Lin Zhu(朱琳), Xing Chen(陈星)

The Hunan Provincial Key Laboratory of Flexible Electronic Materials Genome Engineering, School of Physics&Electronic Science, Changsha University of Science&Technology, Changsha 410114, China

Received:2019-11-06 Revised:2020-03-06 Online:2020-05-05 Published:2020-05-05
Contact: Lijuan Wu E-mail:1329456829@qq.com
Supported by:
Project supported by the Scientific Research Fund of Hunan Provincial Education Department, China (Grant No. 19K001).

摘要/Abstract

摘要： A variable-K trenches silicon-on-insulator (SOI) lateral diffused metal-oxide-semiconductor field-effect transistor (MOSFET) with a double conductive channel is proposed based on the enhancement of low dielectric constant media to electric fields. The device features variable-K dielectric double trenches and a P-pillar between the trenches (VK DT-P LDMOS). The low-K dielectric layer on the surface increases electric field of it. Adding a variable-K material introduces a new electric field peak to the drift region, so as to optimize electric field inside the device. Introduction of the high-concentration vertical P-pillar between the two trenches effectively increases doping concentration of the drift region and maintains charge balance inside it. Thereby, breakdown voltage (BV) of the device is increased. The double conductive channels provide two current paths that significantly reduce specific on-resistance (R_on,sp). Simulation results demonstrate that a 17-μm-length device can achieve a BV of 554 V and a low on-resistance of 13.12 mΩ·cm². The R_on,sp of VK DT-P LDMOS is reduced by 78.9% compared with the conventional structure.

关键词: variable-K (VK), trench technology, specific on-resistance (R_on,sp), breakdown voltage (BV)

Abstract: A variable-K trenches silicon-on-insulator (SOI) lateral diffused metal-oxide-semiconductor field-effect transistor (MOSFET) with a double conductive channel is proposed based on the enhancement of low dielectric constant media to electric fields. The device features variable-K dielectric double trenches and a P-pillar between the trenches (VK DT-P LDMOS). The low-K dielectric layer on the surface increases electric field of it. Adding a variable-K material introduces a new electric field peak to the drift region, so as to optimize electric field inside the device. Introduction of the high-concentration vertical P-pillar between the two trenches effectively increases doping concentration of the drift region and maintains charge balance inside it. Thereby, breakdown voltage (BV) of the device is increased. The double conductive channels provide two current paths that significantly reduce specific on-resistance (R_on,sp). Simulation results demonstrate that a 17-μm-length device can achieve a BV of 554 V and a low on-resistance of 13.12 mΩ·cm². The R_on,sp of VK DT-P LDMOS is reduced by 78.9% compared with the conventional structure.

Key words: variable-K (VK), trench technology, specific on-resistance (R_on,sp), breakdown voltage (BV)

中图分类号: (For silicon electronics)

77.55.df

85.30.De (Semiconductor-device characterization, design, and modeling) 51.50.+v (Electrical properties)

吴丽娟, 朱琳, 陈星. Variable-K double trenches SOI LDMOS with high-concentration P-pillar[J]. 中国物理B, 2020, 29(5): 57701-057701.

Lijuan Wu(吴丽娟), Lin Zhu(朱琳), Xing Chen(陈星). Variable-K double trenches SOI LDMOS with high-concentration P-pillar[J]. Chin. Phys. B, 2020, 29(5): 57701-057701.

参考文献 16

[1]	Zhang W, Qiao M, Wu L, Ye K, Wang Z, Wang Z, Luo X, Zhang S, Su W, Zhang B and Li Z 2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD), May 26-30, 2013, Kanazawa, Japan, 329 doi: International Symposium on Power Semiconductor Devices\|\|
[2]	Qiao M, Jiang L, Wang M. Huang Y, Liao H, Liang T, Sun Z, Zhang B, Li Z, Huang G, Zhao Y, Lai L, Hu X, Zhuang X, Luo X and Wang Z 2011 IEEE 23rd ISPSD, May 23-26, 2011, San Diego, USA, 180
[3]	Li Q, Wen Y, Zhang F, Li H, Xiao G, Chen Y and Fu T 2018 Results Phys. 10 46 doi: 10.1016/j.rinp.2018.05.015
[4]	Xia C, Cheng X H, Wang Z J, Xu D W, Cao D, Zheng L, Shen L Y, Yu Y H and Shen D S 2014 IEEE Trans. Electron. Dev. 61 3477 doi: 10.1109/TED.2014.2349553
[5]	Ge W, Luo X, Wu J, Lv M, Wei J, Ma D, Deng G, Cui W, Yang Y and Zhu K 2017 IEEE Electron Dev. Lett. 38 910 doi: 10.1109/LED.2017.2701354
[6]	Zhang J, Guo Y F, Pan D Z, Yang K M, Lian X J and Yao J F 2018 IEEE Trans. Electron Dev. 65 648 doi: 10.1109/TED.2017.2786139
[7]	Lei J, Hu S, Wang S and Lin Z 2017 Proc. Int. Conf. Electron. Devices Solid-State Circuits (EDSSC), October 18-20, 2017, Hsinchu, Taiwan China, 12
[8]	Luo X R, Lei T F, Wang Y G, Yao G L, Jiang Y H, Zhou K, Wang P, Zhang Z Y, Fan J, Wang Q, Ge R, Zhang B, Li Z and Udrea F 2012 IEEE Trans. Electron Dev. 59 504 doi: 10.1109/TED.2011.2174642
[9]	Luo X R, Fan J, Wang Y G, Lei T F, Qiao M, Zhang B and Udrea F 2011 IEEE Electron Dev. Lett. 32 185 doi: 10.1109/LED.2010.2090938
[10]	Zhou K. Luo X, Xu Q. Lv M, Zhang B and Li Z 2014 IEEE 26th International Symposium on Power Semiconductor Devices & IC's (ISPSD), June 15-19, 2014, Waikoloa, USA, 189 doi: 26th International Symposium on Power Semiconductor Devices\|\|
[11]	Wu L J, Zhang W T, Shi Q, Cai P F and He H C 2014 Electron. Lett. 50 1982 doi: 10.1049/el.2014.3443
[12]	Li H and Chen X 2015 IEEE 11th International Conference on ASIC (ASICON), November 3-6, 2015, Chengdu, China, p. 1
[13]	Luo X R, Udrea F, Wang Y G, Yao G L and Liu Y 2010 IEEE Electron Dev. Lett. 31 594 doi: 10.1109/LED.2010.2046616
[14]	Luo X R, Wang Y G, Deng H, Fan J, Lei T F and Liu Y 2010 IEEE Trans. Electron Dev. 57 535 doi: 10.1109/TED.2009.2037372
[15]	Hu X R, Zhang B, Luo X R, Jiang Y H and Li Z J 2012 Electron Lett. 48 1235 doi: 10.1049/el.2012.1589
[16]	Hu C M 1979 IEEE Trans. Electron Dev. 26 243 doi: 10.1109/T-ED.1979.19416

Variable-K double trenches SOI LDMOS with high-concentration P-pillar

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