Reduction of signal reflection along through silicon via channel in high-speed three-dimensional integration circuit

doi:10.1088/1674-1056/23/3/038401

Abstract The through silicon via (TSV) technology has proven to be the critical enabler to realize a three-dimensional (3D) gigscale system with higher performance but shorter interconnect length. However, the received digital signal after transmission through a TSV channel, composed of redistribution layers (RDLs), TSVs, and bumps, is degraded at a high data-rate due to the non-idealities of the channel. We propose the Chebyshev multisection transformers to reduce the signal reflection of TSV channel when operating frequency goes up to 20 GHz, by which signal reflection coefficient (S₁₁) and signal transmission coefficient (S₂₁) are improved remarkably by 150% and 73.3%, respectively. Both the time delay and power dissipation are also reduced by 4% and 13.3%, respectively. The resistance-inductance-conductance-capacitance (RLGC) elements of the TSV channel are iterated from scattering (S)-parameters, and the proposed method of weakening the signal reflection is verified using high frequency simulator structure (HFSS) simulation software by Ansoft.

Keywords: three-dimensional integrated circuit through silicon via channel signal reflection S-parameters

Received: 21 May 2013
Revised: 18 July 2013
Accepted manuscript online:

PACS:	84.30.-r	(Electronic circuits)
	84.30.Bv	(Circuit theory)

Fund: Project supported by the National Natural Science Foundation of China (Grant No. 61204044).

Corresponding Authors: Liu Xiao-Xian
E-mail: liudou132@163.com

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Liu Xiao-Xian (刘晓贤), Zhu Zhang-Ming (朱樟明), Yang Yin-Tang (杨银堂), Wang Feng-Juan (王凤娟), Ding Rui-Xue (丁瑞雪) Reduction of signal reflection along through silicon via channel in high-speed three-dimensional integration circuit 2014 Chin. Phys. B 23 038401

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Reduction of signal reflection along through silicon via channel in high-speed three-dimensional integration circuit

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