Analytical model including the fringing-induced barrier lowering effect for a dual-material surrounding-gate MOSFET with a high-$\kappa$ gate dielectric

doi:10.1088/1674-1056/21/4/048501

Abstract By solving Poisson's equation in both semiconductor and gate insulator regions in the cylindrical coordinates, an analytical model for a dual-material surrounding-gate (DMSG) metal-oxide semiconductor field-effect transistor (MOSFET) with a high-$\kappa$ gate dielectric has been developed. Using the derived model, the influences of fringing-induced barrier lowering (FIBL) on surface potential, subthreshold current, DIBL, and subthreshold swing are investigated. It is found that for the same equivalent oxide thickness, the gate insulator with high-$\kappa$ dielectric degrades the short-channel performance of the DMSG MOSFET. The accuracy of the analytical model is verified by the good agreement of its results with that obtained from the ISE three-dimensional numerical device simulator.

Keywords: high-$\kappa$ gate dielectric fringing-induced barrier lowering analytical model

Received: 28 September 2011
Revised: 19 December 2011
Accepted manuscript online:

PACS:	85.30.De	(Semiconductor-device characterization, design, and modeling)
	73.40.Qv	(Metal-insulator-semiconductor structures (including semiconductor-to-insulator))
	02.60.Cb	(Numerical simulation; solution of equations)

Fund: Project supported by the Fundamental Research Funds for the Central Universities (Grant No. K50511250001) and the National Natural Science Foundation of China (Grant No. 61076101).

Corresponding Authors: Li Cong,cong.li@mail.xidian.edu.cn
E-mail: cong.li@mail.xidian.edu.cn

Cite this article:

Li Cong(李聪), Zhuang Yi-Qi(庄奕琪), Zhang Li(张丽), and Bao Jun-Lin(包军林) Analytical model including the fringing-induced barrier lowering effect for a dual-material surrounding-gate MOSFET with a high-$\kappa$ gate dielectric 2012 Chin. Phys. B 21 048501

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Analytical model including the fringing-induced barrier lowering effect for a dual-material surrounding-gate MOSFET with a high-$\kappa$ gate dielectric

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