Chip design of a 5.8-GHz fractional-N frequency synthesizer with a tunable Gm–C loop filter

doi:10.1088/1674-1056/21/8/084210

Abstract This paper proposes a novel G_m-C loop filter instead of a conventional passive loop filter used in phase-locked loop. The innovative advantage of the proposed architecture is tunable loop filter bandwidth and hence the process variations of passive elements of resistance R and capacitance C can be overcome and the chip area is greatly reduced. Furthermore the MASH 1-1-1 sigma-delta (Σ Δ) modulator is adopted for performing the fractional division number and hence improves the phase noise as well. Measured results show that the locked phase noise is -114.1 dBc/Hz with lower G_m-C bandwidth and -111.7 dBm/C with higher G_m-C bandwidth at 1 MHz offset from carrier of 5.68 GHz. Including pads and build-in G_m-C filter, the chip area of the proposed frequency synthesizer is 1.06 mm². The output power is -8.69 dBm at 5.68 GHz and consumes 56 mW with off-chip buffer from 1.8-V supply voltage.

Keywords: G_m-C loop filter phase-locked loop PLL voltage-controlled oscillator (VCO)

Received: 10 July 2011
Revised: 11 August 2011
Accepted manuscript online:

PACS:	42.62.Fh
	42.79.Ci	(Filters, zone plates, and polarizers)

Corresponding Authors: Lai Wen-Cheng
E-mail: eway1217@gmail.com

Cite this article:

Huang Jhin-Fang (黄进芳), Liu Ron-Yi (刘荣宜), Lai Wen-Cheng (赖文政), Shin Chun-Wei (石钧纬), Hsu Chien-Ming (许剑铭 ) Chip design of a 5.8-GHz fractional-N frequency synthesizer with a tunable G_m–C loop filter 2012 Chin. Phys. B 21 084210

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Chip design of a 5.8-GHz fractional-N frequency synthesizer with a tunable G_m–C loop filter

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