Analytical capacitance model for 14 nm FinFET considering dual-k spacer

doi:10.1088/1674-1056/26/7/077303

中国物理B ›› 2017, Vol. 26 ›› Issue (7): 77303-077303.doi: 10.1088/1674-1056/26/7/077303

• CONDENSED MATTER: ELECTRONIC STRUCTURE, ELECTRICAL, MAGNETIC, AND OPTICAL PROPERTIES • 上一篇下一篇

Analytical capacitance model for 14 nm FinFET considering dual-k spacer

Fang-Lin Zheng(郑芳林), Cheng-Sheng Liu(刘程晟), Jia-Qi Ren(任佳琪), Yan-Ling Shi(石艳玲), Ya-Bin Sun(孙亚宾), Xiao-Jin Li(李小进)

Shanghai Key Laboratory of Multidimensional Information Processing and the Department of Electrical Engineering, East China Normal University, Shanghai 200241, China

收稿日期:2016-12-13 修回日期:2017-04-11 出版日期:2017-07-05 发布日期:2017-07-05
通讯作者: Xiao-Jin Li E-mail:xjli@ee.ecnu.edu.cn
基金资助:
Project supported by the National Natural Science Foundation of China (Grant Nos.61574056 and 61204038) and the Natural Science Foundation of Shanghai,China (Grant No.14ZR1412000).

Analytical capacitance model for 14 nm FinFET considering dual-k spacer

Fang-Lin Zheng(郑芳林), Cheng-Sheng Liu(刘程晟), Jia-Qi Ren(任佳琪), Yan-Ling Shi(石艳玲), Ya-Bin Sun(孙亚宾), Xiao-Jin Li(李小进)

Shanghai Key Laboratory of Multidimensional Information Processing and the Department of Electrical Engineering, East China Normal University, Shanghai 200241, China

Received:2016-12-13 Revised:2017-04-11 Online:2017-07-05 Published:2017-07-05
Contact: Xiao-Jin Li E-mail:xjli@ee.ecnu.edu.cn
Supported by:
Project supported by the National Natural Science Foundation of China (Grant Nos.61574056 and 61204038) and the Natural Science Foundation of Shanghai,China (Grant No.14ZR1412000).

摘要/Abstract

摘要： The conformal mapping of an electric field has been employed to develop an accurate parasitic capacitance model for nanoscale fin field-effect transistor (FinFET) device. Firstly, the structure of the dual-layer spacers and the gate parasitic capacitors are thoroughly analyzed. Then, the Cartesian coordinate is transferred into the elliptic coordinate and the equivalent fringe capacitance model can be built-up by some arithmetical operations. In order to validate our proposed model, the comparison of statistical analysis between the proposed calculation and the 3D-TCAD simulation has been carried out, and several different material combinations of the dual-k structure have been considered. The results show that the proposed analytical model can accurately calculate the fringe capacitance of the FinFET device with dual-k spacers.

关键词: fin field-effect transistor, parasitic capacitance model, conformal mapping, TCAD

Abstract: The conformal mapping of an electric field has been employed to develop an accurate parasitic capacitance model for nanoscale fin field-effect transistor (FinFET) device. Firstly, the structure of the dual-layer spacers and the gate parasitic capacitors are thoroughly analyzed. Then, the Cartesian coordinate is transferred into the elliptic coordinate and the equivalent fringe capacitance model can be built-up by some arithmetical operations. In order to validate our proposed model, the comparison of statistical analysis between the proposed calculation and the 3D-TCAD simulation has been carried out, and several different material combinations of the dual-k structure have been considered. The results show that the proposed analytical model can accurately calculate the fringe capacitance of the FinFET device with dual-k spacers.

Key words: fin field-effect transistor, parasitic capacitance model, conformal mapping, TCAD

中图分类号: (Metal-insulator-semiconductor structures (including semiconductor-to-insulator))

73.40.Qv

85.30.-z (Semiconductor devices) 77.55.df (For silicon electronics)

郑芳林, 刘程晟, 任佳琪, 石艳玲, 孙亚宾, 李小进. Analytical capacitance model for 14 nm FinFET considering dual-k spacer[J]. 中国物理B, 2017, 26(7): 77303-077303.

Fang-Lin Zheng(郑芳林), Cheng-Sheng Liu(刘程晟), Jia-Qi Ren(任佳琪), Yan-Ling Shi(石艳玲), Ya-Bin Sun(孙亚宾), Xiao-Jin Li(李小进). Analytical capacitance model for 14 nm FinFET considering dual-k spacer[J]. Chin. Phys. B, 2017, 26(7): 77303-077303.

参考文献 18

[1]	Guillorn M, Chang J, Bryant A, et al. 2008 Symposium on VLSI Technology, June 17–19, 2008, Honolulu, USA, p. 12
[2]	Liu F Y, Liu H Z, Liu B W and Guo Y F 2016 Chin. Phys. B 25 047305
[3]	Yu J T, Chen S M, Chen J J and Huang P C 2015 Chin. Phys. B 24 119401
[4]	Fan M M, Xu J P, Liu L, Bai Y R and Huang Y. 2015 Chin. Phys. B 24 037303
[5]	Sun L J, Shang G B Shang, Liu L L, Cheng J, Guo A, Ren Z, Hu S J, Chen S M, Zhao Y H, Chan M, Zhang L, Li X J and Shi Y L 2015 Solid. State. Electron 111 118
[6]	Pandey A, Kumar H, Manhas S K, Dasgupta S and Anand B 2016 IEEE Trans. Electron Devices 63 1392
[7]	Jeong E Y, Yoon J S, Baek C K, Kim Y R, Hong J H, Lee J S, Baek R H and Jeong Y H 2015 IEEE Trans. Electron Devices 62 3441
[8]	Khakifirooz A and Antoniadis D A 2006 International Electron Devices Meeting December 11–13, 2006, San Francisco, USA, p. 1
[9]	Pal P K, Kaushik B K and Dasgupta S 2015 IEEE Trans. Electron Devices 62 1105
[10]	Liu X, Jin X S and Lee J H 2009 Solid. State. Electron 53 1041
[11]	Lee K W, An T Y, Joo S Y, Kwon K W and Kim S Y 2013 IEEE Trans. Electron Devices 60 1786
[12]	Chauhan Y S, Lu D D and Sriramkumar V 2015 FinFET Modeling for IC Simulation and Design:Using the BSIM-CMG Standard (London:Academic Press) p. 157
[13]	Lacord J, Ghibaudo G and Boeuf F 2012 IEEE Trans. Electron Devices 59 1332
[14]	Lacord J, Martinie S, Rozeau O, Jaud M A, Barraud S and Barbé J C 2016 IEEE Trans. Electron Devices 63 781
[15]	Bansal A, Paul B C and Roy K 2006 IEEE Trans. Comput. Des. Integr. Circuits Syst. 25 2765
[16]	Synopsys Inc. Sentaurus TCAD manuals,[Online] Available:http://www.synopsys.com
[17]	Iwai H 2015 Solid. State. Electron. 112 56
[18]	Mark B 2014 Intel Developer Forum

Analytical capacitance model for 14 nm FinFET considering dual-k spacer

Analytical capacitance model for 14 nm FinFET considering dual-k spacer

RichHTML

PDF (PC)

赞

可视化

摘要/Abstract

引用本文

使用本文

参考文献 18

相关文章 15

Metrics

本文评价

推荐阅读 0

[1]	Hong Zhang(张鸿), Hongxia Guo(郭红霞), Zhifeng Lei(雷志锋), Chao Peng(彭超), Zhangang Zhang(张战刚), Ziwen Chen(陈资文), Changhao Sun(孙常皓), Yujuan He(何玉娟), Fengqi Zhang(张凤祁), Xiaoyu Pan(潘霄宇), Xiangli Zhong(钟向丽), and Xiaoping Ouyang(欧阳晓平). Experiment and simulation on degradation and burnout mechanisms of SiC MOSFET under heavy ion irradiation[J]. 中国物理B, 2023, 32(2): 28504-028504.
[2]	Dong-Qing Li(李东青), Tian-Qi Liu(刘天奇), Pei-Xiong Zhao(赵培雄), Zhen-Yu Wu(吴振宇), Tie-Shan Wang(王铁山), and Jie Liu(刘杰). Strategy to mitigate single event upset in 14-nm CMOS bulk FinFET technology[J]. 中国物理B, 2022, 31(5): 56106-056106.
[3]	Ying Hu(胡颖), Jiaping Wang(王家平), Peng Zhao(赵鹏), Zhenhua Lin(林珍华), Siyu Zhang(张思玉), Jie Su(苏杰), Miao Zhang(张苗), Jincheng Zhang(张进成), Jingjing Chang(常晶晶), and Yue Hao(郝跃). Reveal the large open-circuit voltage deficit of all-inorganicCsPbIBr₂ perovskite solar cells[J]. 中国物理B, 2022, 31(3): 38804-038804.
[4]	Shao-Hua Yang(杨少华), Zhan-Gang Zhang(张战刚), Zhi-Feng Lei(雷志锋), Yun Huang(黄云), Kai Xi(习凯), Song-Lin Wang(王松林), Tian-Jiao Liang(梁天骄), Teng Tong(童腾), Xiao-Hui Li(李晓辉), Chao Peng(彭超), Fu-Gen Wu(吴福根), and Bin Li(李斌). Impact of incident direction on neutron-induced single-bit and multiple-cell upsets in 14 nm FinFET and 65 nm planar SRAMs[J]. 中国物理B, 2022, 31(12): 126103-126103.
[5]	Manhong Zhang(张满红) and Wanchen Wu(武万琛). An insulated-gate bipolar transistor model based on the finite-volume charge method[J]. 中国物理B, 2022, 31(12): 128501-128501.
[6]	Hong Zhang(张鸿), Hong-Xia Guo(郭红霞), Feng-Qi Zhang(张凤祁), Xiao-Yu Pan(潘霄宇), Yi-Tian Liu(柳奕天), Zhao-Qiao Gu(顾朝桥), An-An Ju(琚安安), and Xiao-Ping Ouyang(欧阳晓平). Sensitivity of heavy-ion-induced single event burnout in SiC MOSFET[J]. 中国物理B, 2022, 31(1): 18501-018501.
[7]	Jia-Jia Zhang(张佳佳), Peng Ding(丁芃), Ya-Nan Jin(靳雅楠), Sheng-Hao Meng(孟圣皓), Xiang-Qian Zhao(赵向前), Yan-Fei Hu(胡彦飞), Ying-Hui Zhong(钟英辉), and Zhi Jin(金智). A comparative study on radiation reliability of composite channel InP high electron mobility transistors[J]. 中国物理B, 2021, 30(7): 70702-070702.
[8]	Jia-Xin Wang(王加鑫), Xiao-Jing Li(李晓静), Fa-Zhan Zhao(赵发展), Chuan-Bin Zeng(曾传滨), Duo-Li Li(李多力), Lin-Chun Gao(高林春), Jiang-Jiang Li(李江江), Bo Li(李博), Zheng-Sheng Han(韩郑生), and Jia-Jun Luo(罗家俊). Trigger mechanism of PDSOI NMOS devices for ESD protection operating under elevated temperatures[J]. 中国物理B, 2021, 30(7): 78501-078501.
[9]	Yang-Tong Yu(俞扬同), Xue-Qiang Xiang(向学强), Xuan-Ze Zhou(周选择), Kai Zhou(周凯), Guang-Wei Xu(徐光伟), Xiao-Long Zhao(赵晓龙), and Shi-Bing Long(龙世兵). Device topological thermal management of β-Ga₂O₃ Schottky barrier diodes[J]. 中国物理B, 2021, 30(6): 67302-067302.
[10]	费新星, 王颖, 罗昕, 于成浩. Simulation study of high voltage GaN MISFETs with embedded PN junction[J]. 中国物理B, 2020, 29(8): 80701-080701.
[11]	章合坤, 田璇, 何俊鹏, 宋哲, 蔚倩倩, 李靓, 李明, 赵连城, 高立明. Investigation of gate oxide traps effect on NAND flash memory by TCAD simulation[J]. 中国物理B, 2020, 29(3): 38501-038501.
[12]	魏佳男, 贺朝会, 李培, 李永宏, 郭红霞. Impact of proton-induced alteration of carrier lifetime on single-event transient in SiGe heterojunction bipolar transistor[J]. 中国物理B, 2019, 28(7): 76106-076106.
[13]	魏佳男, 贺朝会, 李培, 李永宏. Research on SEE mitigation techniques using back junction and p⁺ buffer layer in domestic non-DTI SiGe HBTs by TCAD[J]. 中国物理B, 2019, 28(6): 68503-068503.
[14]	汪志刚, 廖涛, 王亚南. Modeling electric field of power metal-oxide-semiconductor field-effect transistor with dielectric trench based on Schwarz-Christoffel transformation[J]. 中国物理B, 2019, 28(5): 58503-058503.
[15]	潘霄宇, 郭红霞, 罗尹虹, 张凤祁, 丁李利, 魏佳男, 赵雯. Impact of neutron-induced displacement damage on the single event latchup sensitivity of bulk CMOS SRAM[J]. 中国物理B, 2017, 26(1): 18501-018501.