Trigger mechanism of PDSOI NMOS devices for ESD protection operating under elevated temperatures

doi:10.1088/1674-1056/abe2fe

中国物理B ›› 2021, Vol. 30 ›› Issue (7): 78501-078501.doi: 10.1088/1674-1056/abe2fe

Trigger mechanism of PDSOI NMOS devices for ESD protection operating under elevated temperatures

Jia-Xin Wang(王加鑫)^1,2,3, Xiao-Jing Li(李晓静)^1,2,†, Fa-Zhan Zhao(赵发展)^1,2,‡, Chuan-Bin Zeng(曾传滨)^1,2, Duo-Li Li(李多力)^1,2, Lin-Chun Gao(高林春)^1,2, Jiang-Jiang Li(李江江)^1,2, Bo Li(李博)^1,2, Zheng-Sheng Han(韩郑生)^1,2,3, and Jia-Jun Luo(罗家俊)^1,2

1 Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China;
2 Key Laboratory of Science and Technology on Silicon Devices, Chinese Academy of Sciences, Beijing 100029, China;
3 University of Chinese Academy of Sciences, Beijing 100029, China

收稿日期:2020-11-09 修回日期:2021-01-04 接受日期:2021-02-04 出版日期:2021-06-22 发布日期:2021-07-09
通讯作者: Xiao-Jing Li, Fa-Zhan Zhao E-mail:lixiaojing1@ime.ac.cn;zhaofazhan@ime.ac.cn
基金资助:
Project supported by the National Natural Science Foundation of China (Grant No. 61804168).

Trigger mechanism of PDSOI NMOS devices for ESD protection operating under elevated temperatures

1 Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China;
2 Key Laboratory of Science and Technology on Silicon Devices, Chinese Academy of Sciences, Beijing 100029, China;
3 University of Chinese Academy of Sciences, Beijing 100029, China

Received:2020-11-09 Revised:2021-01-04 Accepted:2021-02-04 Online:2021-06-22 Published:2021-07-09
Contact: Xiao-Jing Li, Fa-Zhan Zhao E-mail:lixiaojing1@ime.ac.cn;zhaofazhan@ime.ac.cn
Supported by:
Project supported by the National Natural Science Foundation of China (Grant No. 61804168).

摘要/Abstract

摘要： Trigger characteristics of electrostatic discharge (ESD) protecting devices operating under various ambient temperatures ranging from 30 ℃ to 195 ℃ are investigated. The studied ESD protecting devices are the H-gate NMOS transistors fabricated with a 0.18-μm partially depleted silicon-on-insulator (PDSOI) technology. The measurements are conducted by using a transmission line pulse (TLP) test system. The different temperature-dependent trigger characteristics of grounded-gate (GGNMOS) mode and the gate-triggered (GTNMOS) mode are analyzed in detail. The underlying physical mechanisms related to the effect of temperature on the first breakdown voltage V_T1 are investigated through the assist of technology computer-aided design (TCAD) simulation.

关键词: ESD, trigger voltage, temperature, GGNMOS, GTNMOS, TCAD

Abstract: Trigger characteristics of electrostatic discharge (ESD) protecting devices operating under various ambient temperatures ranging from 30 ℃ to 195 ℃ are investigated. The studied ESD protecting devices are the H-gate NMOS transistors fabricated with a 0.18-μm partially depleted silicon-on-insulator (PDSOI) technology. The measurements are conducted by using a transmission line pulse (TLP) test system. The different temperature-dependent trigger characteristics of grounded-gate (GGNMOS) mode and the gate-triggered (GTNMOS) mode are analyzed in detail. The underlying physical mechanisms related to the effect of temperature on the first breakdown voltage V_T1 are investigated through the assist of technology computer-aided design (TCAD) simulation.

Key words: ESD, trigger voltage, temperature, GGNMOS, GTNMOS, TCAD

中图分类号: (Semiconductor-device characterization, design, and modeling)

85.30.De

41.20.Cv (Electrostatics; Poisson and Laplace equations, boundary-value problems) 85.30.Mn (Junction breakdown and tunneling devices (including resonance tunneling devices))

Jia-Xin Wang(王加鑫), Xiao-Jing Li(李晓静), Fa-Zhan Zhao(赵发展), Chuan-Bin Zeng(曾传滨), Duo-Li Li(李多力), Lin-Chun Gao(高林春), Jiang-Jiang Li(李江江), Bo Li(李博), Zheng-Sheng Han(韩郑生), and Jia-Jun Luo(罗家俊). Trigger mechanism of PDSOI NMOS devices for ESD protection operating under elevated temperatures[J]. 中国物理B, 2021, 30(7): 78501-078501.

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Trigger mechanism of PDSOI NMOS devices for ESD protection operating under elevated temperatures

Trigger mechanism of PDSOI NMOS devices for ESD protection operating under elevated temperatures

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