中国物理B ›› 2012, Vol. 21 ›› Issue (6): 68501-068501.doi: 10.1088/1674-1056/21/6/068501

• INTERDISCIPLINARY PHYSICS AND RELATED AREAS OF SCIENCE AND TECHNOLOGY • 上一篇    下一篇

A low on-resistance triple RESURF SOI LDMOS with planar and trench gate integration

罗小蓉a b, 姚国亮a, 张正元b, 蒋永恒a, 周坤a, 王沛a, 王元刚a, 雷天飞a, 张云轩a, 魏杰a   

  1. a. State Key Laboratory of Electronic Thin Films and Integrated Devices. University of Electronic Science and Technology of China, Chengdu 610054, China;
    b. No. 24 Research Institute of China Electronics Technology Group Corporation, Chongqing 400060, China
  • 收稿日期:2011-09-23 修回日期:2011-11-17 出版日期:2012-05-01 发布日期:2012-05-01
  • 基金资助:
    Project supported by the National Natural Science Foundation of China (Grant Nos. 61176069 and 609 76060) and the National Key Laboratory of Analogue Integrated Circuit (Grant No. 9140C090304110C0905).

A low on-resistance triple RESURF SOI LDMOS with planar and trench gate integration

Luo Xiao-Rong(罗小蓉)a)b)†, Yao Guo-Liang(姚国亮)a), Zhang Zheng-Yuan(张正元)b), Jiang Yong-Heng(蒋永恒)a), Zhou Kun(周坤)a), Wang Pei(王沛)a), Wang Yuan-Gang(王元刚) a), Lei Tian-Fei(雷天飞)a), Zhang Yun-Xuan(张云轩)a), and Wei Jie(魏杰)a)   

  1. a. State Key Laboratory of Electronic Thin Films and Integrated Devices. University of Electronic Science and Technology of China, Chengdu 610054, China;
    b. No. 24 Research Institute of China Electronics Technology Group Corporation, Chongqing 400060, China
  • Received:2011-09-23 Revised:2011-11-17 Online:2012-05-01 Published:2012-05-01
  • Contact: Luo Xiao-Rong E-mail:xrluo@uestc.edu.cn
  • Supported by:
    Project supported by the National Natural Science Foundation of China (Grant Nos. 61176069 and 609 76060) and the National Key Laboratory of Analogue Integrated Circuit (Grant No. 9140C090304110C0905).

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摘要： A low on-resistance (Ron,sp) integrable silicon-on-insulator (SOI) n-channel lateral double-diffused metal-oxide-semiconductor (LDMOS) is proposed and its mechanism is investigated by simulation. The LDMOS has two features: the integration of a planar gate and an extended trench gate (double gates (DGs)); and a buried P-layer in the N-drift region, which forms a triple reduced surface field (RESURF) (TR) structure. The triple RESURF not only modulates the electric field distribution, but also increases N-drift doping, resulting in a reduced specific on-resistance (Ron,sp) and an improved breakdown voltage (BV) in the off-state. The DGs form dual conduction channels and, moreover, the extended trench gate widens the vertical conduction area, both of which further reduce the Ron,sp. The BV and Ron,sp are 328 V and 8.8 mΩ·cm2, respectively, for a DG TR metal-oxide-semiconductor field-effect transistor (MOSFET) by simulation. Compared with a conventional SOI LDMOS, a DG TR MOSFET with the same dimensional device parameters as those of the DG TR MOSFET reduces Ron,sp by 59% and increases BV by 6%. The extended trench gate synchronously acts as an isolation trench between the high-voltage device and low-voltage circuitry in a high-voltage integrated circuit, thereby saving the chip area and simplifying the fabrication processes.

关键词: SOI, electric field, breakdown voltage, trench gate, specific on-resistance

Abstract: A low on-resistance (Ron,sp) integrable silicon-on-insulator (SOI) n-channel lateral double-diffused metal-oxide-semiconductor (LDMOS) is proposed and its mechanism is investigated by simulation. The LDMOS has two features: the integration of a planar gate and an extended trench gate (double gates (DGs)); and a buried P-layer in the N-drift region, which forms a triple reduced surface field (RESURF) (TR) structure. The triple RESURF not only modulates the electric field distribution, but also increases N-drift doping, resulting in a reduced specific on-resistance (Ron,sp) and an improved breakdown voltage (BV) in the off-state. The DGs form dual conduction channels and, moreover, the extended trench gate widens the vertical conduction area, both of which further reduce the Ron,sp. The BV and Ron,sp are 328 V and 8.8 mΩ·cm2, respectively, for a DG TR metal-oxide-semiconductor field-effect transistor (MOSFET) by simulation. Compared with a conventional SOI LDMOS, a DG TR MOSFET with the same dimensional device parameters as those of the DG TR MOSFET reduces Ron,sp by 59% and increases BV by 6%. The extended trench gate synchronously acts as an isolation trench between the high-voltage device and low-voltage circuitry in a high-voltage integrated circuit, thereby saving the chip area and simplifying the fabrication processes.

Key words: SOI, electric field, breakdown voltage, trench gate, specific on-resistance

中图分类号:  (Semiconductor-device characterization, design, and modeling)

  • 85.30.De
85.30.Tv (Field effect devices)