A low on-resistance triple RESURF SOI LDMOS with planar and trench gate integration
罗小蓉, 姚国亮, 张正元, 蒋永恒, 周坤, 王沛, 王元刚, 雷天飞, 张云轩, 魏杰
A low on-resistance triple RESURF SOI LDMOS with planar and trench gate integration
Luo Xiao-Rong(罗小蓉), Yao Guo-Liang(姚国亮), Zhang Zheng-Yuan(张正元), Jiang Yong-Heng(蒋永恒), Zhou Kun(周坤), Wang Pei(王沛), Wang Yuan-Gang(王元刚), Lei Tian-Fei(雷天飞), Zhang Yun-Xuan(张云轩), and Wei Jie(魏杰)
中国物理B
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2012, (6): 68501
-068501
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DOI: 10.1088/1674-1056/21/6/068501