中国物理B ›› 2012, Vol. 21 ›› Issue (6): 68501-068501.doi: 10.1088/1674-1056/21/6/068501
• INTERDISCIPLINARY PHYSICS AND RELATED AREAS OF SCIENCE AND TECHNOLOGY • 上一篇 下一篇
罗小蓉a b, 姚国亮a, 张正元b, 蒋永恒a, 周坤a, 王沛a, 王元刚a, 雷天飞a, 张云轩a, 魏杰a
Luo Xiao-Rong(罗小蓉)a)b)†, Yao Guo-Liang(姚国亮)a), Zhang Zheng-Yuan(张正元)b), Jiang Yong-Heng(蒋永恒)a), Zhou Kun(周坤)a), Wang Pei(王沛)a), Wang Yuan-Gang(王元刚) a), Lei Tian-Fei(雷天飞)a), Zhang Yun-Xuan(张云轩)a), and Wei Jie(魏杰)a)
摘要: A low on-resistance (Ron,sp) integrable silicon-on-insulator (SOI) n-channel lateral double-diffused metal-oxide-semiconductor (LDMOS) is proposed and its mechanism is investigated by simulation. The LDMOS has two features: the integration of a planar gate and an extended trench gate (double gates (DGs)); and a buried P-layer in the N-drift region, which forms a triple reduced surface field (RESURF) (TR) structure. The triple RESURF not only modulates the electric field distribution, but also increases N-drift doping, resulting in a reduced specific on-resistance (Ron,sp) and an improved breakdown voltage (BV) in the off-state. The DGs form dual conduction channels and, moreover, the extended trench gate widens the vertical conduction area, both of which further reduce the Ron,sp. The BV and Ron,sp are 328 V and 8.8 mΩ·cm2, respectively, for a DG TR metal-oxide-semiconductor field-effect transistor (MOSFET) by simulation. Compared with a conventional SOI LDMOS, a DG TR MOSFET with the same dimensional device parameters as those of the DG TR MOSFET reduces Ron,sp by 59% and increases BV by 6%. The extended trench gate synchronously acts as an isolation trench between the high-voltage device and low-voltage circuitry in a high-voltage integrated circuit, thereby saving the chip area and simplifying the fabrication processes.
中图分类号: (Semiconductor-device characterization, design, and modeling)