›› 2014, Vol. 23 ›› Issue (8): 88501-088501.doi: 10.1088/1674-1056/23/8/088501
• SPECIAL TOPI—International Conference on Nanoscience & Technology, China 2013 • 上一篇 下一篇
褚玉琼a, 张满红b, 霍宗亮a, 刘明a
Chu Yu-Qiong (褚玉琼)a, Zhang Man-Hong (张满红)b, Huo Zong-Liang (霍宗亮)a, Liu Ming (刘明)a
摘要: In this paper the endurance characteristics and trap generation are investigated to study the effects of different post-deposition anneals (PDAs) on the integrity of an Al2O3/Si3N4/SiO2/Si memory gate stack. The flat-band voltage (Vfb) turnarounds are observed in both the programmed and erased states of the N2-PDA device. In contrast, this turnaround is observed only in the erased state of the O2-PDA device. The Vfb in the programmed state of the O2-PDA device keeps increasing with increasing program/erase (P/E) cycles. Through the analyses of endurance characteristics and the low voltage round-trip current transients, it is concluded that in both kinds of device there are an unknown type of pre-existing characteristic deep traps and P/E stress-induced positive oxide charges. In the O2-PDA device two extra types of trap are also found: the pre-existing border traps and the P/E stress-induced negative traps. Based on these four types of defects we can explain the endurance characteristics of two kinds of device. The switching property of pre-existing characteristic deep traps is also discussed.
中图分类号: (Semiconductor devices)