中国物理B ›› 2013, Vol. 22 ›› Issue (6): 67306-067306.doi: 10.1088/1674-1056/22/6/067306

• CONDENSED MATTER: ELECTRONIC STRUCTURE, ELECTRICAL, MAGNETIC, AND OPTICAL PROPERTIES • 上一篇    下一篇

A low on-resistance buried current path SOI p-channel LDMOS compatible with n-channel LDMOS

周坤, 罗小蓉, 范远航, 罗尹春, 胡夏融, 张波   

  1. State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu 610054, China
  • 收稿日期:2012-08-09 修回日期:2013-01-05 出版日期:2013-05-01 发布日期:2013-05-01
  • 基金资助:
    Project supported by the National Natural Science Foundation of China (Grant No. 61176069), the State Key Laboratory Science Fund of Electronic Thin Films and Integrated Devices of China (Grant No. CXJJ201004), and the National Key Laboratory Science Fund of Analog Integrated Circuit, China (Grant No. 9140C090304110C0905).

A low on-resistance buried current path SOI p-channel LDMOS compatible with n-channel LDMOS

Zhou Kun (周坤), Luo Xiao-Rong (罗小蓉), Fan Yuan-Hang (范远航), Luo Yin-Chun (罗尹春), Hu Xia-Rong (胡夏融), Zhang Bo (张波)   

  1. State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu 610054, China
  • Received:2012-08-09 Revised:2013-01-05 Online:2013-05-01 Published:2013-05-01
  • Contact: Luo Xiao-Rong E-mail:xrluo@uestc.edu.cn
  • Supported by:
    Project supported by the National Natural Science Foundation of China (Grant No. 61176069), the State Key Laboratory Science Fund of Electronic Thin Films and Integrated Devices of China (Grant No. CXJJ201004), and the National Key Laboratory Science Fund of Analog Integrated Circuit, China (Grant No. 9140C090304110C0905).

PDF (PC)

794

赞

摘要： A novel low specific on-resistance (Ron,sp) silicon-on-insulator (SOI) p-channel lateral double-diffused metal-oxide semiconductor (pLDMOS) compatible with high voltage (HV) n-channel LDMOS (nLDMOS) is proposed. The pLDMOS is built in the N-type SOI layer with a buried P-type layer acting as a current conduction path in the on-state (BP SOI pLDMOS). Its superior compatibility with the HV nLDMOS and low voltage (LV) complementary metal-oxide semiconductor (CMOS) circuitry which are formed on the N-SOI layer can be obtained. In the off-state the P-buried layer built in the N-SOI layer causes multiple depletion and electric field reshaping, leading to an enhanced (reduced surface field) (RESURF) effect. The proposed BP SOI pLDMOS achieves not only an improved breakdown voltage (BV) but also a significantly reduced Ron,sp. The BV of the BP SOI pLDMOS increases to 319 V from 215 V of the conventional SOI pLDMOS at the same half cell pitch of 25 μ, and Ron,sp decreases from 157 mΩ·cm2 to 55 mΩ·cm2. Compared with the PW SOI pLDMOS, the BP SOI pLDMOS also reduces the Ron,sp by 34% with almost the same BV.

关键词: silicon-on-insulator, p-channel LDMOS, p-buried layer, breakdown voltage

Abstract: A novel low specific on-resistance (Ron,sp) silicon-on-insulator (SOI) p-channel lateral double-diffused metal-oxide semiconductor (pLDMOS) compatible with high voltage (HV) n-channel LDMOS (nLDMOS) is proposed. The pLDMOS is built in the N-type SOI layer with a buried P-type layer acting as a current conduction path in the on-state (BP SOI pLDMOS). Its superior compatibility with the HV nLDMOS and low voltage (LV) complementary metal-oxide semiconductor (CMOS) circuitry which are formed on the N-SOI layer can be obtained. In the off-state the P-buried layer built in the N-SOI layer causes multiple depletion and electric field reshaping, leading to an enhanced (reduced surface field) (RESURF) effect. The proposed BP SOI pLDMOS achieves not only an improved breakdown voltage (BV) but also a significantly reduced Ron,sp. The BV of the BP SOI pLDMOS increases to 319 V from 215 V of the conventional SOI pLDMOS at the same half cell pitch of 25 μ, and Ron,sp decreases from 157 mΩ·cm2 to 55 mΩ·cm2. Compared with the PW SOI pLDMOS, the BP SOI pLDMOS also reduces the Ron,sp by 34% with almost the same BV.

Key words: silicon-on-insulator, p-channel LDMOS, p-buried layer, breakdown voltage

中图分类号:  (Semiconductor-insulator-semiconductor structures)

  • 73.40.Ty
73.90.+f (Other topics in electronic structure and electrical properties of surfaces, interfaces, thin films, and low-dimensional structures) 73.61.Ng (Insulators)