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Low switching loss and increased short-circuit capability split-gate SiC trench MOSFET with p-type pillar |
| Pei Shen(沈培)1,2, Ying Wang(王颖)1,†, Xing-Ji Li(李兴冀)3, Jian-Qun Yang(杨剑群)3, and Fei Cao(曹菲)1 |
1 The School of Electronic Information, Hangzhou Dianzi University, Hangzhou 310018, China;
2 The School of Mechanical and Electronic Engineering, Pingxiang University, Pingxiang 337055, China;
3 The National Key Laboratory of Materials Behavior and Evaluation Technology in Space Environment, Harbin Institute of Technology, Harbin 150080, China |
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Abstract A split-gate SiC trench gate MOSFET with stepped thick oxide, source-connected split-gate (SG), and p-type pillar (p-pillar) surrounded thick oxide shielding region (GSDP-TMOS) is investigated by Silvaco TCAD simulations. The source-connected SG region and p-pillar shielding region are introduced to form an effective two-level shielding, which reduces the specific gate-drain charge ($Q_{\rm gd,sp}$) and the saturation current, thus reducing the switching loss and increasing the short-circuit capability. The thick oxide that surrounds a p-pillar shielding region efficiently protects gate oxide from being damaged by peaked electric field, thereby increasing the breakdown voltage ($BV$). Additionally, because of the high concentration in the n-type drift region, the electrons diffuse rapidly and the specific on-resistance ($R_{\rm on,sp}$) becomes smaller. In the end, comparing with the bottom p$^{+}$ shielded trench MOSFET (GP-TMOS), the Baliga figure of merit (BFOM, $BV^{2}/R_{\rm on,sp}$) is increased by 169.6%, and the high-frequency figure of merit (HF-FOM, $R_{\rm on,sp}\times Q_{\rm gd,sp}$) is improved by 310%, respectively.
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Received: 16 August 2022
Revised: 08 October 2022
Accepted manuscript online: 10 October 2022
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PACS:
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85.30.-z
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(Semiconductor devices)
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85.30.De
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(Semiconductor-device characterization, design, and modeling)
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| Fund: Project supported by the National Natural Science Foundation of China (Grant Nos. 61774052 and 61904045), the National Research and Development Program for Major Research Instruments of China (Grant No. 62027814), and the Natural Science Foundation of Jiangxi Province, China (Grant No. 20212BAB214047). |
Corresponding Authors:
Ying Wang
E-mail: wangying7711@yahoo.com
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Cite this article:
Pei Shen(沈培), Ying Wang(王颖), Xing-Ji Li(李兴冀), Jian-Qun Yang(杨剑群), and Fei Cao(曹菲) Low switching loss and increased short-circuit capability split-gate SiC trench MOSFET with p-type pillar 2023 Chin. Phys. B 32 058501
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