The tunnel field-effect transistor (TFET) is proposed by using the advantages of dopingless and line-tunneling technology. The line tunneling is created due to the fact that the gate electric field is aligned with the tunneling direction, which dramatically enhances tunneling area and tunneling current. Moreover, the effects of the structure parameters such as the length between top gate and source electrode, the length between top gate and drain electrode, the distance between bottom gate and drain electrode, and the metal position on the on-state current, electric field and energy band are investigated and optimized. In addition, analog/radio-frequency performance and linearity characteristics are studied. All results demonstrate that the proposed device not only enhances the on/of current ratio and reduces the subthreshold swing, but also offers eight times improvement in cut-off frequency and gain band product as compared with the conventional point tunneling dopingless TFET, at the same time; it shows better linearity and small distortions. This proposed device greatly enhances the potential of applications in dopingless TFET.
* Project supported by the Natural Science Research Key Project of Universities of Anhui Province, China (Grant No. KJ2017A502), the Introduced Talent Project of Anhui Science and Technology University, China (Grant No. DQYJ201603), and the Excellent Talents Supported Project of Colleges and Universities, China (Grant No. gxyq2018048).
Cite this article:
Hui-Fang Xu(许会芳)†, Xin-Feng Han(韩新风), and Wen Sun(孙雯) Design and investigation of dopingless double-gate line tunneling transistor: Analog performance, linearity, and harmonic distortion analysis 2020 Chin. Phys. B 29 108502
Fig. 1.
Structure of devices of (a) PT−DLTFET, (b) LT−DLTFET, and (c) M−LT−DLTFET.
Parameter
Symbol
PT−DLTFET
LT−DLTFET
M−LT−DLTFET
Top gate length
LTG
55 nm
55 nm
55 nm
Bottom gate length
LBG
55 nm
50 nm
50 nm
Source length
LS
20 nm
20 nm
20 nm
Drain length
LD
20 nm
20 nm
20 nm
Distance between top gate and source electrode
LTGS
5 nm
5 nm
5 nm
Distance between top gate and drain electrode
LTGD
10 nm
10 nm
10 nm
Distance between bottom gate and drain electrode
LBGD
10 nm
20 nm
20 nm
Oxide layer thickness
TOX
3 nm
3 nm
3 nm
Ge body thickness
TGe
10 nm
10 nm
10 nm
Top gate work function
WKTG
4.2 eV
3.9 eV
3.9 eV
Bottom gate work function
WKBG
4.2 eV
4.6 eV
4.6 eV
Metal work function
WKM
3.9 eV
Source electrode work function
WKS
5.9 eV
5.9 eV
5.9 eV
Drain electrode work function
WKD
3.9 eV
3.9 eV
3.9 eV
Table 1.
Material parameters and dimensions of devices.
Fig. 2.
Plot of energy varying with distance for M−LT−DLTFET along (a) A–A’ direction, and (b) B–B’ direction under on-state condition, (c) plots of electron and hole concentrations varying with top-bottom distance along B–B’ direction under on-state condition.
Fig. 3.
(a) Electric field varying with distance along cutline A–A’, (b) electron current density varying with distance along cutline A–A’, (c) transfer characteristics, and (d) extracted SS varying with Ids for the devices.
Parameter
PT_DLTFET
LT_DLTFET
M_LT_DLTFET
Ion/(A/μm)
1.90117×10−6
4.44004×10−6
1.14652×10−5
Ion/Ioff
4.19×108
9.81×108
1.48×109
Iamb/(A/μm)
5.01×10−15
4.69×10−15
4.67×10−15
SSavg/(mV/dec)
72.52
44.07
34.15
SSmin/(mV/dec)
27.47
29.36
26.23
Vth/V
0.34
0.2
0.16
Table 2.
Comparison of DC parameter among devices.
Fig. 4.
Plots of energy varying with distance at different values of LTGS (a) along cutline A–A’ when Vgs is fixed at 0.2 V, (b) along cutline A–A’ when Vgs is fixed at 1 V, (c) along cutline B–B’ when Vgs is fixed at 0.2 V, and (d) along cutline B–B’ when Vgs is fixed at 1 V.
Fig. 5.
(a) Transfer characteristics, and (b) electric fields varying with distance along A–A’ direction for proposed device with different distances between source and top-gate electrode.
Fig. 6.
(a) Transfer characteristics, and (b) energy varying with distance along A–A’ direction for proposed device with different distances between top-gate and drain electrode.
Fig. 7.
Plots of energyvarying with distance along (a) A–A’, and (b) C–C’ direction for proposed device with different distances between bottom-gate and drain electrode.
Fig. 8.
Plots of IdsversusVgs for M−LT−DLTFET with metal at different positions along (a) x direction and (b) y direction, (c) for different work functions of metal.
Fig. 9.
Plots of (a) gm, (b) Cgd, (c) CggversusVgs for three devices.
Fig. 10.
RF parameters of (a) ft, (b) GBP, and (c) TFP for three devices.
Fig. 11.
Plots of (a) gm2, and (b) gm3versusVgs for three devices.
Fig. 12.
Linearity parameters of (a) VIP2, (b) VIP3, (c) IIP3, and (d) IMD3 for three devices.
Fig. 13.
Plots of (a) HD2, and (b) HD3versusVgs for three devices.
[1]
Eshaan B, Kaushal N, Shubham C, Savitesh C 2019 Micro & Nano Lett. 14 1238 DOI: 10.1049/mnl.2019.0252
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