An interconnecting bus power optimization method combining interconnect wire spacing with wire ordering

doi:10.1088/1674-1056/20/6/068401

Abstract On-chip interconnect buses consume tens of percents of dynamic power in a nanometer scale integrated circuit and they will consume more power with the rapid scaling down of technology size and continuously rising clock frequency, therefore it is meaningful to lower the interconnecting bus power in design. In this paper, a simple yet accurate interconnect parasitic capacitance model is presented first and then, based on this model, a novel interconnecting bus optimization method is proposed. Wire spacing is a process for spacing wires for minimum dynamic power, while wire ordering is a process that searches for wire orders that maximally enhance it. The method, i.e., combining wire spacing with wire ordering, focuses on bus dynamic power optimization with a consideration of bus performance requirements. The optimization method is verified based on various nanometer technology parameters, showing that with 50% slack of routing space, 25.71% and 32.65% of power can be saved on average by the proposed optimization method for a global bus and an intermediate bus, respectively, under a 65-nm technology node, compared with 21.78% and 27.68% of power saved on average by uniform spacing technology. The proposed method is especially suitable for computer-aided design of nanometer scale on-chip buses.

Keywords: interconnect bus dynamic power wire ordering wire spacing nanometer scale process

Received: 18 September 2010
Revised: 20 December 2010
Accepted manuscript online:

PACS:	84.30.-r	(Electronic circuits)
	84.30.Bv	(Circuit theory)

Fund: Project supported by the National Natural Science Foundation of China (Grant Nos. 60725415, 60971066, and 61006028), the National High-Tech Program of China (Grant Nos. 2009AA01Z258 and 2009AA01Z260), and the National Key Lab Foundation, China (Grant No. ZHD200904).

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Zhu Zhang-Ming (朱樟明), Hao Bao-Tian (郝报田), En Yun-Fei (恩云飞), Yang Yin-Tang (杨银堂), Li Yue-Jin (李跃进) An interconnecting bus power optimization method combining interconnect wire spacing with wire ordering 2011 Chin. Phys. B 20 068401

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An interconnecting bus power optimization method combining interconnect wire spacing with wire ordering

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