Analysis of tail bits generation of multilevel storage in resistive switching memory

doi:10.1088/1674-1056/27/11/118501

Abstract

The tail bits of intermediate resistance states (IRSs) achieved in the SET process (IRS^S) and the RESET process (IRS^R) of conductive-bridge random-access memory were investigated. Two types of tail bits were observed, depending on the filament morphology after the SET/RESET operation. (i) Tail bits resulting from lateral diffusion of Cu ions introduced an abrupt increase of device resistance from IRS to ultrahigh-resistance state, which mainly happened in IRS^S. (ii) Tail bits induced by the vertical diffusion of Cu ions showed a gradual shift of resistance toward lower value. Statistical results show that more than 95% of tail bits are generated in IRS^S. To achieve a reliable IRS for multilevel cell (MLC) operation, it is desirable to program the IRS in RESET operation. The mechanism of tail bit generation that is disclosed here provides a clear guideline for the data retention optimization of MLC resistive random-access memory cells.

Keywords: resistive random-access memory (RRAM) multilevel cell tail bits

Received: 23 August 2018
Revised: 19 October 2018
Accepted manuscript online:

PACS:	85.30.De	(Semiconductor-device characterization, design, and modeling)
	83.85.Ns	(Data analysis (interconversion of data computation of relaxation and retardation spectra; time-temperature superposition, etc.))
	85.40.Qx	(Microcircuit quality, noise, performance, and failure analysis)

Fund:

Project supported by the Ministry of Science and Technology of China (Grant Nos. 2016YFA0203800, 2016YFA0201803, and 2018YFB0407502), the National Natural Science Foundation of China (Grant Nos. 61522408, 61334007, and 61521064), Beijing Municipal Science & Technology Commission Program, China (Grant No. Z161100000216153), and Huawei Data Center Technology Laboratory.

Corresponding Authors: Xiaoxin Xu, Hangbing Lv
E-mail: xuxiaoxin@ime.ac.cn;lvhangbing@ime.ac.cn

Cite this article:

Jing Liu(刘璟), Xiaoxin Xu(许晓欣), Chuanbing Chen(陈传兵), Tiancheng Gong(龚天成), Zhaoan Yu(余兆安), Qing Luo(罗庆), Peng Yuan(袁鹏), Danian Dong(董大年), Qi Liu(刘琦), Shibing Long(龙世兵), Hangbing Lv(吕杭炳), Ming Liu(刘明) Analysis of tail bits generation of multilevel storage in resistive switching memory 2018 Chin. Phys. B 27 118501

[1]	Waser R and Aono M 2007 Nat. Mater. 6 833
[2]	Wu Q Q, Chen J, Luo J X, Lu K, Chai Z, Yu T and Wang X 2013 Chin. Phys. Lett. 30 068502
[3]	Lu N, Sun P, Li L, Liu Q, Long S, Lv H and Liu M 2016 Chin. Phys. B 25 056501
[4]	Deng N, Jia H Y, Wu W and Wu H Q 2014 Chin. Phys. Lett. 31 108504
[5]	Wu M C, Lin Y W, Jang W Y, Lin C H and Tseng T Y 2012 IEEE Electron. Dev. Lett. 32 1026
[6]	Gilbert N E and Kozicki M N 2007 IEEE J. Solid-State Circuits 42 6
[7]	Chen B, Kang J F and Huang P 2013 IEEE VLSI Technology (VLSIT), 2013 Symposium on, Kyoto, Japan, 11-13 June 2013, p. 545591
[8]	Lee H Y, Chen P S and Wu T Y 2008 IEEE Intrnational Electron Devices Meeting, San Francisco, CA, USA, 15-17 December 2008, p. 1
[9]	Yu S M, Wu Y and Wong H S P 2011 Appl. Phys. Lett. 98 103514
[10]	Zhao L, Chen H Y and Wu S C 2014 Proc. Technicl Program-2014 International Symposium on VLSI Technology, Systems and Application, Hsinchu, Taiwan, 28-30 April 2014, p. 6839673
[11]	Zangeneh M and Joshi A 2014 IEEE Transactions on Very Large Scale Integration Systems 22 1815
[12]	Ielmini D, Nardi F and Cagli C 2010 IEEE Electron. Dev. Lett. 31 353
[13]	Choi S, Lee J and Jim S 2014 Appl. Phys. Lett. 105 113510
[14]	Xue K H and Miao X S 2018 J. Appl. Phys. 123 161505
[15]	Ielmini D 2011 IEEE Intrnational Electron Devices Meeting, Washington, DC, USA, 5-7 December 2011, p. 17.2.1
[16]	Pérez E, Grossi A and Zambelli C 2017 IEEE Electron. Dev. Lett. 38 175
[17]	Lv H B, Xu X X, Liu H T, Liu R Y, Liu Q, Banerjee W, Sun H T, Long S B, Li L and Liu M 2015 Sci. Rep. 5 7764
[18]	Wu S J, Wang F, Zhang Z C, Li Y, Han Y M, Yang Z C, Zhao J S and Zhang K L 2018 Chin. Phys. B 27 087701
[19]	Chen C Y, Fantini A, Goux L, Degraeve R, Clima S, Redolfi A, Groeseneken G and Jurczak M 2015 IEEE Intrnational Electron Devices Meeting, Washington, DC, USA, 7-9 December 2015, p. 10.6.1
[20]	Huang X, Wu H, Gao B, Sekar D C, Dai L, Kellam M, Bronner G, Deng N and Qian H 2016 Nanotechnology 27 395201
[21]	Sekar D C, Bateman B, Raghuram U, Bowyer S, Bai Y, Calarrudo M, Swab P, Wu J, Nguyen S, Mishra N, Meyer R, Kellam M, Chevallier C, Wu H Q, Qian H, Kreupl F and Bronner G 2014 IEEE Intrnational Electron Devices Meeting, San Francisco, CA, USA, 15-17 December 2014, p. 28.3.1

[1]	SPICE modeling of memristors with multilevel resistance states Fang Xu-Dong (方旭东), Tang Yu-Hua (唐玉华), Wu Jun-Jie (吴俊杰). Chin. Phys. B, 2012, 21(9): 098901.
[2]	Bipolar resistive switching in Cr-doped TiO_x thin films Xing Zhong-Wen(邢钟文), X. Chen, N. J. Wu, and A. Ignatiev . Chin. Phys. B, 2011, 20(9): 097703.

No Suggested Reading articles found!

Viewed

Full text

Abstract

Cited

Metrics
Related Articles

Analysis of tail bits generation of multilevel storage in resistive switching memory

Cite this article:

Online attention