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Modeling of the drain-induced barrier lowering effect and optimization for a dual-channel 4H silicon carbide metal semiconductor field effect transistor |
Zhang Xian-Jun(张现军)†, Yang Yin-Tang(杨银堂), Duan Bao-Xing(段宝兴), Chai ChangChun(柴常春), Song Kun(宋坤), and Chen-Bin(陈斌) |
Key Laboratory of Wide Band Gap Semiconductor Materials and Devices of the Ministry of Education, School of Microelectronics, Xidian University, Xi’an 710071, China |
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Abstract A new analytical model to describe the drain-induced barrier lowering (DIBL) effect has been obtained by solving the two-dimensional (2D) Poisson's equation for the dual-channel 4H-SiC MESFET (DCFET). Using this analytical model, we calculate the threshold voltage shift and the sub-threshold slope factor of the DCFET, which characterize the DIBL effect. The results show that they are significantly dependent on the drain bias, gate length as well as the thickness and doping concentration of the two channel layers. Based on this analytical model, the structure parameters of the DCFET have been optimized in order to suppress the DIBL effect and improve the performance.
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Received: 31 March 2012
Revised: 31 March 2012
Accepted manuscript online:
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PACS:
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73.40.Jn
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(Metal-to-metal contacts)
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85.30.Tv
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(Field effect devices)
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85.30.De
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(Semiconductor-device characterization, design, and modeling)
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Fund: Project supported by the Pre-research Foundation from the National Ministries and Commissions of China (Grant No. 51308030201). |
Corresponding Authors:
Zhang Xian-Jun,xianjun_zhang@yahoo.com.cn
E-mail: xianjun_zhang@yahoo.com.cn
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Cite this article:
Zhang Xian-Jun(张现军), Yang Yin-Tang(杨银堂), Duan Bao-Xing(段宝兴), Chai ChangChun(柴常春), Song Kun(宋坤), and Chen-Bin(陈斌) Modeling of the drain-induced barrier lowering effect and optimization for a dual-channel 4H silicon carbide metal semiconductor field effect transistor 2012 Chin. Phys. B 21 037303
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