中国物理B ›› 2025, Vol. 34 ›› Issue (6): 68501-068501.doi: 10.1088/1674-1056/adc40b
Yuanhao Bi(毕元昊)1, Dajing Bian(卞大井)1, Ming Li(李铭)1, and Yue Xu(徐跃)1,2,†
Yuanhao Bi(毕元昊)1, Dajing Bian(卞大井)1, Ming Li(李铭)1, and Yue Xu(徐跃)1,2,†
摘要: A near-infrared (NIR) enhanced silicon single-photon avalanche diode (SPAD) detector is proposed using 0.18 μm bipolar-CMOS-DMOS technology. It is based on a deep multiplication region, formed by a junction between the high-voltage P-well (HVPW) and high-voltage buried N$+$ layer, to enhance the NIR photon detection probability (PDP). Thanks to the lightly doped P-type epitaxial layer, the electric field in the guard ring is reduced and premature breakdown is prevented. In particular, an extra P-type implantation layer (PIL) is added to the HVPW to reduce the breakdown voltage and enhance the device's sensitivity. Further research on the impact of different PIL sizes on the device performance is carried out. It is experimentally shown that at an excess bias voltage of 5 V, the optimized SPAD achieves a dark count rate of 0.64 cps/μm$^2$, peak PDP of 54.8% at 555 nm and PDP of 10.53% at 905 nm. The full width at half-maximum of the timing jitter is 285 ps, and the afterpulsing probability is lower than 1.17%. This novel device provides a practical, low-cost solution for high-performance NIR time-of-flight detectors and 3D imaging sensors.
中图分类号: (Semiconductor-device characterization, design, and modeling)