中国物理B ›› 2015, Vol. 24 ›› Issue (12): 127305-127305.doi: 10.1088/1674-1056/24/12/127305

• CONDENSED MATTER: ELECTRONIC STRUCTURE, ELECTRICAL, MAGNETIC, AND OPTICAL PROPERTIES • 上一篇    下一篇

Influence of ultra-thin TiN thickness (1.4 nm and 2.4 nm) on positive bias temperature instability (PBTI) of high-k/metal gate nMOSFETs with gate-last process

祁路伟, 杨红, 任尚清, 徐烨峰, 罗维春, 徐昊, 王艳蓉, 唐波, 王文武, 闫江, 朱慧珑, 赵超, 陈大鹏, 叶甜春   

  1. Key Laboratory of Microelectronics Devices and Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China
  • 收稿日期:2015-06-26 修回日期:2015-07-27 出版日期:2015-12-05 发布日期:2015-12-05
  • 通讯作者: Qi Lu-Wei E-mail:qiluwei@ime.ac.cn
  • 基金资助:
    Project supported by the National High Technology Research and Development Program of China (Grant No. SS2015AA010601) and the National Natural Science Foundation of China (Grant Nos. 61176091 and 61306129).

Influence of ultra-thin TiN thickness (1.4 nm and 2.4 nm) on positive bias temperature instability (PBTI) of high-k/metal gate nMOSFETs with gate-last process

Qi Lu-Wei (祁路伟), Yang Hong (杨红), Ren Shang-Qing (任尚清), Xu Ye-Feng (徐烨峰), Luo Wei-Chun (罗维春), Xu Hao (徐昊), Wang Yan-Rong (王艳蓉), Tang Bo (唐波), Wang Wen-Wu (王文武), Yan Jiang (闫江), Zhu Hui-Long (朱慧珑), Zhao Chao (赵超), Chen Da-Peng (陈大鹏), Ye Tian-Chun (叶甜春)   

  1. Key Laboratory of Microelectronics Devices and Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China
  • Received:2015-06-26 Revised:2015-07-27 Online:2015-12-05 Published:2015-12-05
  • Contact: Qi Lu-Wei E-mail:qiluwei@ime.ac.cn
  • Supported by:
    Project supported by the National High Technology Research and Development Program of China (Grant No. SS2015AA010601) and the National Natural Science Foundation of China (Grant Nos. 61176091 and 61306129).

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摘要： The positive bias temperature instability (PBTI) degradations of high-k/metal gate (HK/MG) nMOSFETs with thin TiN capping layers (1.4 nm and 2.4 nm) are systemically investigated. In this paper, the trap energy distribution in gate stack during PBTI stress is extracted by using ramped recovery stress, and the temperature dependences of PBTI (90 ℃, 125 ℃, 160 ℃) are studied and activation energy (Ea) values (0.13 eV and 0.15 eV) are extracted. Although the equivalent oxide thickness (EOT) values of two TiN thickness values are almost similar (0.85 nm and 0.87 nm), the 2.4-nm TiN one (thicker TiN capping layer) shows better PBTI reliability (13.41% at 0.9 V, 90 ℃, 1000 s). This is due to the better interfacial layer/high-k (IL/HK) interface, and HK bulk states exhibited through extracting activation energy and trap energy distribution in the high-k layer.

关键词: positive bias temperature instability (PBTI), HK/MG, Ea, trap energy distribution

Abstract: The positive bias temperature instability (PBTI) degradations of high-k/metal gate (HK/MG) nMOSFETs with thin TiN capping layers (1.4 nm and 2.4 nm) are systemically investigated. In this paper, the trap energy distribution in gate stack during PBTI stress is extracted by using ramped recovery stress, and the temperature dependences of PBTI (90 ℃, 125 ℃, 160 ℃) are studied and activation energy (Ea) values (0.13 eV and 0.15 eV) are extracted. Although the equivalent oxide thickness (EOT) values of two TiN thickness values are almost similar (0.85 nm and 0.87 nm), the 2.4-nm TiN one (thicker TiN capping layer) shows better PBTI reliability (13.41% at 0.9 V, 90 ℃, 1000 s). This is due to the better interfacial layer/high-k (IL/HK) interface, and HK bulk states exhibited through extracting activation energy and trap energy distribution in the high-k layer.

Key words: positive bias temperature instability (PBTI), HK/MG, Ea, trap energy distribution

中图分类号:  (Metal-insulator-semiconductor structures (including semiconductor-to-insulator))

  • 73.40.Qv
85.30.Tv (Field effect devices)