中国物理B ›› 2021, Vol. 30 ›› Issue (4): 47103-.doi: 10.1088/1674-1056/abccba

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  • 收稿日期:2020-10-15 修回日期:2020-11-12 接受日期:2020-11-23 出版日期:2021-03-16 发布日期:2021-04-02

Analysis on degradation mechanisms of normally-off p-GaN gate AlGaN/GaN high-electron mobility transistor

Si-De Song(宋思德), Su-Zhen Wu(吴素贞), Guo-Zhu Liu(刘国柱), Wei Zhao(赵伟), Yin-Quan Wang(王印权), Jian-Wei Wu(吴建伟), and Qi He(贺琪)   

  1. 1 The 58 th Institution of Electronic Science and Technology Group Corporation of China, Wuxi 214000, China
  • Received:2020-10-15 Revised:2020-11-12 Accepted:2020-11-23 Online:2021-03-16 Published:2021-04-02
  • Contact: Corresponding author. E-mail: cetc_songsd@163.com
  • Supported by:
    Project supported by the Equipment Developing Advanced Research Program of China (Grant No. 6140A24030107).

Abstract: The degradation mechanisms of enhancement-mode p-GaN gate AlGaN/GaN high-electron mobility transistor was analyzed extensively, by means of drain voltage stress and gate bias stress. The results indicate that: (i) High constant drain voltage stress has only a negligible impact on the device electrical parameters, with a slightly first increase and then decrease in output current; (ii) A negative shift of threshold voltage and increased output current were observed in the device subjected to forward gate bias stress, which is mainly ascribed to the hole-trapping induced by high electric field across the p-GaN/AlGaN interface; (iii) The analyzed device showed an excellent behavior at reverse gate bias stress, with almost unaltered threshold voltage, output current, and gate leakage current, exhibiting a large gate swing in the negative direction. The results are meaningful and valuable in directing the process optimization towards a high voltage and high reliable enhanced AlGaN/GaN high-electron mobility transistor.

Key words: high-electron-mobility transistors (HEMTs), stress, degradation, threshold voltage

中图分类号:  (III-V semiconductors)

  • 71.55.Eq
73.50.Gr (Charge carriers: generation, recombination, lifetime, trapping, mean free paths) 73.40.Kp (III-V semiconductor-to-semiconductor contacts, p-n junctions, and heterojunctions) 85.30.De (Semiconductor-device characterization, design, and modeling)