中国物理B ›› 2012, Vol. 21 ›› Issue (5): 57304-057304.doi: 10.1088/1674-1056/21/5/057304
马飞,刘红侠,匡潜玮,樊继斌
Ma Fei(马飞)†, Liu Hong-Xia(刘红侠), Kuang Qian-Wei(匡潜玮), and Fan Ji-Bin(樊继斌)
摘要: We investigate the influence of voltage drop across the lightly doped drain (LDD) region and the built-in potential on MOSFETs, and develop a threshold voltage model for high-k gate dielectric MOSFETs with fully overlapped LDD structures by solving the two-dimensional Poisson's equation in the silicon and gate dielectric layers. The model can predict the fringing-induced barrier lowering effect and the short channel effect. It is also valid for non-LDD MOSFETs. Based on this model, the relationship between threshold voltage roll-off and three parameters, channel length, drain voltage and gate dielectric permittivity, is investigated. Compared with the non-LDD MOSFET, the LDD MOSFET depends slightly on channel length, drain voltage, and gate dielectric permittivity. The model is verified at the end of the paper.
中图分类号: (Metal-insulator-semiconductor structures (including semiconductor-to-insulator))