A novel sensitivity model for short nets

doi:10.1088/1674-1056/21/9/098503

Abstract For modern processes at deep sub-micron technology node, yield design, especially the yield design at the stage of layout design is an important way to deal with the problem about manufacturability and yield. In order to reduce the yield loss caused by redundancy material defect, choice of nets to be optimized at first is an important step in the process of layout optimization. This paper provides a new sensitivity model for short net, which is net-based and reflects the size of the critical area between a single net and the nets around it. Since this model is based on a single net and includes the information of surrounding nets，the critical area between the single net and surrounding nets can be reduced at the same time. In this way, the efficiency of layout optimization becomes higher. According to experimental observations, this sensitivity model can be used to choose the position for optimization. Compared with the chip-area-based and basic-layout-based sensitivity models, our sensitivity model not only has higher efficiency, but also hold true for choosing the net to be optimized at first.

Keywords: redundancy material defect layout optimization critical area short sensitivity

Received: 19 December 2011
Revised: 25 April 2012
Accepted manuscript online:

PACS:	85.40.Bh	(Computer-aided design of microcircuits; layout and modeling)
	61.72.-y	(Defects and impurities in crystals; microstructure)

Fund: Project supported by the National Natural Science Foundation of China (Grant Nos. 61173088 and 61070143) and the Programme of Introducing Talents of Discipline to Universities (Grant No. B08038)

Corresponding Authors: Liu Shi-Gang
E-mail: shi72385588@163.com

Cite this article:

Liu Shi-Gang (刘士钢), Wang Jun-Ping (王俊平), Su Yong-Bang (苏永邦), Wang Le (王乐) A novel sensitivity model for short nets 2012 Chin. Phys. B 21 098503

[1]	Suiter G and Isaac J 2009 Circ. Tree 22 16
[2]	Raghvendra S and Hurat P 2005 Proceedings of the 18th International Conference on VLSI Design January 3-7, 2005 Kolkata, India, pp. 705-708
[3]	Chiang C and Kawa J 2006IEEE Asia Pacific Conference on Circuits and Systems December 4-7, 2006 Singapore, pp. 1099-1102
[4]	Gopalani S, Garg R, Khatri S P and Cheng M S 2009 The 12th International Symposium on Integrated Circuits December 14-16, 2009 Singapore, pp. 29-32
[5]	Muller D 2006 IEEE/ACM International Conference on Computer-Aided Design November 5-9, 2006 San Jose, USA, pp. 480-486
[6]	Cho M, Xiang H, Puri R and Pan D Z 2008 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 27 872
[7]	Kahng A B, Liu B and Mandoiu I I 2002 International Conference on Computer Aided Design November 10-14, 2002 Freiburg, Germany, pp. 260-266
[8]	Su J Z and Dai W 1997 International Conference on Computer Aided Design November 9-13, 1997 California, USA, pp. 700-706
[9]	Sinha S, Su Q, Wen L N, Lee F, Chiang C, Cheng Y K, Lin J L and Harn Y C 2008 IEEE Trans. Semicond. Manufac. 21 14
[10]	Chen H Y, Chou S J, Wang S L and Chang Y W 2009 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 28 193
[11]	Cho M, Xiang H, Puri R and Pan D Z 2006 International Conference on Computer-Aided Design November 5-9, 2006 San Jose, USA, 487
[12]	Shen Y, Zhou Q, Cai Y C and Hong X L 2010 IEEE Trans. VLSI Syst. 18 153
[13]	Pan D Z, Cho M and Yuan K 2010 Foundations and Trends in Electronic Design Automation 4 1
[14]	Mead C and Conway L 1980 Introduction to VLSI Systems (New Jersey: Wesley Addison Pub.) p. 390
[15]	Cong J 2006 International Conference on Computer-Aided Design November 5-9, 2006 San Jose, USA, p. l15
[16]	Cross D, Nequist E and Scheffer L 2007 International Symposium on Physical Design March 18-21, 2007 Texas, USA
[17]	Zhu Z M, Wan D J and Yang Y T 2010 Acta Phys. Sin. 59 4842 (in Chinese)
[18]	Dong G, Liu J, Xue M and Yang Y T 2011 Acta Phys. Sin. 60 046602 (in Chinese)
[19]	Wang J P and HaoY 2005 Chin. J. Semicond. 26 1514 (in Chinese)
[20]	Wang J P, Hao Y, Zang J M, Ren G L and Ni H 2008 The 2nd International Conference on Anti-counterfeiting, Security and Identification August 20-23, 2008 Guiyang, China, pp. 313-315
[21]	Zhu Z M, Hao B T, Li R and Yang Y T 2010 Acta Phys. Sin. 59 2003 (in Chinese)
[22]	Yao H, Sinha S, Xu J, Chiang C, Cai Y and Hong X 2008 Circuits, Devices and Systems, IET 2 2
[23]	Cho M, Yuan K, Ban Y and Pan D Z 2009 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 28 1006
[24]	Goel H and Dance D 2003 Advanced Semiconductor Manufacturing Conference and Workshop IEEEI/SEMI March 31-April 1, 2003 Munich, German, pp. 262-265
[25]	BarNt T S, Bickford J and Weger A J 2007 IEEE Trans. Semicond. Manufac. 21 351
[26]	Ducotey G, Couvrat A, Audran V, Pepper D, Couturier L and David D 2008 Advanced Semiconductor Manufacturing Conference May 5-7, 2008 pp. 138-141
[27]	Izuka T, Ikeda M and Asada K 2007 IEEE Trans. VLSI Syst. 15 716
[28]	Wang J P and Hao Y 2006 Chin. Phys. 15 1621
[29]	Wang J P, Hao Y and Zhang J M 2007 Chin. Phys. 16 1796
[30]	Porat R, Dotan K, Hemar S, Levin L, Li K, Sung G, Lin C T, Lin S K and Wang H I 2008 Advanced Semiconductor Manufacturing Conference May 5-7, 2008 Massachusetts, USA, p. 11
[31]	Scott J, Glenn F, Alexa P and Steven F 2008 Advanced Semiconductor Manufacturing Conference May 5-7, 2008 Massachusetts, USA, pp. 69-71
[32]	DeVries D K and Simon P L C 2003 The 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems November 3-5, 2003 Massachusetts, USA, pp. 26-33
[33]	Zachariah S T and Chakravarty S 2003 IEEE Trans. VLSI Syst. 11 741
[34]	Nag P K and Maly W 1995 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems November 13-15, 1995 Lafayette, USA, pp. 19-27
[35]	Goncalves F M, Teixeira I C and Teixeira J P 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems November 6-8, 1996 pp. 96-104
[36]	Zachariah S T and Chakravarty S 2000 IEEE Test Conference October 3-5, 2000 Philadelphia, USA, pp. 750-759
[37]	Wang J P and Hao Y 2009 Acta Phys. Sin. 58 4267 (in Chinese)
[38]	Rani G, Ken S D and Pay Z H 2009 IEEE Trans. Semicond. Manufac. 22 329
[39]	Wang J P, Ning P, Wang L, Su Y B, Liu S G, Wan G T and Wang S 2010 The 2nd International Conference on Information Engineering and Computer Science December 25-26, 2010 Wuhan, China, pp. 1-3

[1]	Open critical area model and extraction algorithm based on the net flow-axis Wang Le (王乐), Wang Jun-Ping (王俊平), Gao Yan-Hong (高艳红), Xu Dan (许丹), Li Bo-Bo (李玻玻), Liu Shi-Gang (刘士钢). Chin. Phys. B, 2013, 22(12): 128504.
[2]	Yield estimation of metallic layers in integrated circuits Wang Jun-Ping(王俊平), Hao Yue(郝跃), and Zhang Jun-Ming(张俊明). Chin. Phys. B, 2007, 16(6): 1796-1805.
[3]	Critical area computation for real defects and arbitrary conductor shapes Wang Jun-Ping (王俊平), Hao Yue (郝跃). Chin. Phys. B, 2006, 15(7): 1621-1630.

No Suggested Reading articles found!

Viewed

Full text

Abstract

Cited

Metrics
Related Articles

A novel sensitivity model for short nets

Cite this article:

Online attention