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Chinese Physics, 2007, Vol. 16(6): 1796-1805    DOI: 10.1088/1009-1963/16/6/054
CROSS DISCIPLINARY PHYSICS AND RELATED AREAS OF SCIENCE AND TECHNOLOGY Prev   Next  

Yield estimation of metallic layers in integrated circuits

Wang Jun-Ping(王俊平), Hao Yue(郝跃), and Zhang Jun-Ming(张俊明)
Microelectronics Institute, Key Laboratory of Ministry of Education for Wide Band-Gap Semiconductor Materials and Devices, Xidian University, Xi'an 710071, China
Abstract  In the existing models of estimating the yield and critical area, the defect outline is usually assumed to be circular, but the observed real defect outlines are irregular in shape. In this paper, estimation of the yield and critical area is made using the Monte Carlo technique and the relationship between the errors of yield estimated by circular defect and the rectangle degree of the defect is analysed. The rectangular model of a real defect is presented, and the yield model is provided correspondingly. The models take into account an outline similar to that of an original defect, the characteristics of two-dimensional distribution of defects, the feature of a layout routing, and the character of yield estimation. In order to make the models practicable, the critical area computations related to rectangular defect and regular (vertical or horizontal) routing are discussed. The critical areas associated with rectangular defect and non-regular routing are developed also, based on the mathematical morphology. The experimental results show that the new yield model may predict the yield caused by real defects more accurately than the circular model. It is significant that the yield is accurately estimated using the proposed model for IC metals.
Keywords:  real defects      critical area model      mathematical morphology      yield estimation  
Received:  08 August 2006      Revised:  09 January 2007      Accepted manuscript online: 
PACS:  85.40.Bh (Computer-aided design of microcircuits; layout and modeling)  
Fund: Project supported by Xi'an Applied Materials Innovation Fund (Grant No XA-AM-200601) and National Laboratory on Machine Perception of Peking University Fund (Grant No 0604).

Cite this article: 

Wang Jun-Ping(王俊平), Hao Yue(郝跃), and Zhang Jun-Ming(张俊明) Yield estimation of metallic layers in integrated circuits 2007 Chinese Physics 16 1796

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