Abstract Repeater optimization is the key for SOC (System on Chip) interconnect delay design. This paper proposes a novel optimal model for minimizing power and area overhead of repeaters while meeting the target performance of on-chip interconnect lines. It also presents Lagrangian function to find the number of repeaters and their sizes required for minimizing area and power overhead with target delay constraint. Based on the 65 nanometre CMOS technology, the computed results of the intermediate and global lines show that the proposed model can significantly reduce area and power of interconnected lines, and the better performance will be achieved with the longer line. The results compared with the reference paper demonstrate the validity of this model. It can be integrated into repeater design methodology and CAD (computer aided design) tool for interconnect planning in nanometre SOC.
Received: 17 June 2008
Revised: 04 September 2008
Accepted manuscript online:
Fund: Project supported by the National
Natural Science Foundation of the China (Grant Nos 60676009 and
60776034), the Doctor Foundation of Ministry of Education of China
(Grant No 20050701015), and the National Outstanding Young Scientist
Foundation of China
Cite this article:
Zhu Zhang-Ming(朱樟明), Qian Li-Bo(钱利波), and Yang Yin-Tang(杨银堂) A novel interconnect-optimal repeater insertion model with target delay constraint in 65nm CMOS 2009 Chin. Phys. B 18 1188
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