Impact of STI indium implantation on reliability of gate oxide

doi:10.1088/1674-1056/ac0e26

中国物理B ›› 2022, Vol. 31 ›› Issue (2): 28505-028505.doi: 10.1088/1674-1056/ac0e26

Impact of STI indium implantation on reliability of gate oxide

Xiao-Liang Chen(陈晓亮)^1,2,†, Tian Chen(陈天)², Wei-Feng Sun(孙伟锋)¹, Zhong-Jian Qian(钱忠健)², Yu-Dai Li(李玉岱)², and Xing-Cheng Jin(金兴成)²

1 National ASIC System Engineering Research Center, School of Electronic Science & Engineering, Southeast University, Nanjing 210096, China;
2 China Resources Microelectronics Co., Ltd, China

收稿日期:2021-05-20 修回日期:2021-06-18 接受日期:2021-06-24 出版日期:2022-01-13 发布日期:2022-01-13
通讯作者: Xiao-Liang Chen E-mail:chenxiaoliang2@crmicro.com

Impact of STI indium implantation on reliability of gate oxide

Xiao-Liang Chen(陈晓亮)^1,2,†, Tian Chen(陈天)², Wei-Feng Sun(孙伟锋)¹, Zhong-Jian Qian(钱忠健)², Yu-Dai Li(李玉岱)², and Xing-Cheng Jin(金兴成)²

1 National ASIC System Engineering Research Center, School of Electronic Science & Engineering, Southeast University, Nanjing 210096, China;
2 China Resources Microelectronics Co., Ltd, China

Received:2021-05-20 Revised:2021-06-18 Accepted:2021-06-24 Online:2022-01-13 Published:2022-01-13
Contact: Xiao-Liang Chen E-mail:chenxiaoliang2@crmicro.com

摘要/Abstract

摘要： The impacts of shallow trench isolation (STI) indium implantation on gate oxide and device characteristics are studied in this work. The stress modulation effect is confirmed in this research work. An enhanced gate oxide oxidation rate is observed due to the enhanced tensile stress, and the thickness gap is around 5%. Wafers with and without STI indium implantation are manufactured using the 150-nm silicon on insulator (SOI) process. The ramped voltage stress and time to breakdown capability of the gate oxide are researched. No early failure is observed for both wafers the first time the voltage is ramped up. However, a time dependent dielectric breakdown (TDDB) test shows more obvious evidence that the gate oxide quality is weakened by the STI indium implantation. Meanwhile, the device characteristics are compared, and the difference between two devices is consistent with the equivalent oxide thickness (EOT) gap.

关键词: silicon-on-insulator, shallow trench isolation (STI) implantation, gate oxide reliability

Abstract: The impacts of shallow trench isolation (STI) indium implantation on gate oxide and device characteristics are studied in this work. The stress modulation effect is confirmed in this research work. An enhanced gate oxide oxidation rate is observed due to the enhanced tensile stress, and the thickness gap is around 5%. Wafers with and without STI indium implantation are manufactured using the 150-nm silicon on insulator (SOI) process. The ramped voltage stress and time to breakdown capability of the gate oxide are researched. No early failure is observed for both wafers the first time the voltage is ramped up. However, a time dependent dielectric breakdown (TDDB) test shows more obvious evidence that the gate oxide quality is weakened by the STI indium implantation. Meanwhile, the device characteristics are compared, and the difference between two devices is consistent with the equivalent oxide thickness (EOT) gap.

Key words: silicon-on-insulator, shallow trench isolation (STI) implantation, gate oxide reliability

中图分类号: (Field effect devices)

85.30.Tv

61.80.Ed (γ-ray effects) 85.40.Ry (Impurity doping, diffusion and ion implantation technology)

Xiao-Liang Chen(陈晓亮), Tian Chen(陈天), Wei-Feng Sun(孙伟锋), Zhong-Jian Qian(钱忠健), Yu-Dai Li(李玉岱), and Xing-Cheng Jin(金兴成). Impact of STI indium implantation on reliability of gate oxide[J]. 中国物理B, 2022, 31(2): 28505-028505.

参考文献

[1] Pelloie J L 2003 Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting, October 28, 2003, Toulouse, France, pp. 151-155
[2] Dai L H, Bi D W, Hu Z Y, Liu X N, Zhang M Y, Zhang Z X and Zou S C 2018 Chin. Phys. B 27 048503
[3] Fan S, Hu Z Y, Zhang Z X, Ning B X, Bi D W, Dai L H, Zhang M Y and Zhang L Q 2017 Chin. Phys. B 26 036103
[4] Colinge J P 2004 Silicon-on-insulator technology:materials to VLSI, 3rd edn. (New York:Springer) pp. 309-312
[5] Peng C, Hu Z Y, En Y F, Chen Y Q, Lei Z F, Zhang Z G, Zhang Z G and Li B 2018 IEEE Trans. Nucl. Sci. 65 877
[6] Zebrev G I and Gorbunov M S 2009 IEEE Trans. Nucl. Sci. 56 2230
[7] Xi S X, Zheng Q W, Lu W, Cui J W, Wei Y and Guo Q 2020 Microelectronics Journal 102 104829
[8] Ning B X, Zhang Z X, Liu Z L, Hu Z Y, Chen M, Bi D W and Zou S C 2012 Microelectronics Reliability 52 130
[9] Li D M, Wang Z H, Huangpu L Y and Gou Q J 2007 Chin. Phys. B 16 3760
[10] Chatzikyriakou E, Morgan K and Kees de Groot C H 2018 IEEE Transactions on Electron Devices 65 808
[11] Lee W T and Elgin Q 2012 U.S. Patent 7 592 270 (2012-2-21)
[12] Ortolland C, Morin P, Chaton C, Mastromatteo E, Populaire C, Orain S, Leverd F, Stolk P, Boeuf F and Arnaud F C 2006 Symposium on VLSI Technology, June 13-15, 2006, Honolulu, USA, pp. 78-79
[13] Doremus R H and Szewczyk A 1987 Journal of Materials Science 22 2887
[14] Doremus R H 1976 Journal of Physical Chemistry 80 1773
[15] Mott N F 1983 Proceedings of the Fifth International Symposium on Passivity, May 30-June 3, 1983, Bombannes, France, pp. 1-9
[16] Irene E A 1982 Journal of the Electrochemical Society 129 413
[17] Randriamihaja Y M, Huard V, Zaka A, Haendler S, Federspiel X, Rafik M, Rideau D, Roy D and Bravaix A 2011 International Reliability Physics Symposium, April 10-14, 2011, Monterey, USA, pp. GD.3.1-GD.3.4
[18] Kaczer B, Franco J and Weckx P 2018 Microelectronics Reliability 81 186
[19] Zhang W D, Zhang J F, Zhao C Z, Chang M H, Groeseneken G and Degraeve R 2006 IEEE Electron Device Lett. 27 393
[20] Xu M and Tan C 2009 IEEE Electron Device Lett. 30 410
[21] Gupta A, Peng F, Song M, Lin M R, Wollesen D, Chen K and Hu C 1997 IEEE Electron Device Lett. 18 580

Impact of STI indium implantation on reliability of gate oxide

Impact of STI indium implantation on reliability of gate oxide

RichHTML

PDF (PC)

赞

可视化

摘要/Abstract

引用本文

使用本文

参考文献

相关文章 15

Metrics

本文评价

推荐阅读 0

[1]	刘先程, 马佳俊, 谢红云, 马佩, 陈亮, 郭敏, 张万荣. Effects of buried oxide layer on working speed of SiGe heterojunction photo-transistor[J]. 中国物理B, 2020, 29(2): 28501-028501.
[2]	戴丽华, 毕大炜, 胡志远, 刘小年, 张梦映, 张正选, 邹世昌. Research on the radiation hardened SOI devices with single-step Si ion implantation[J]. 中国物理B, 2018, 27(4): 48503-048503.
[3]	张梦映, 胡志远, 毕大炜, 戴丽华, 张正选. Enhanced radiation-induced narrow channel effects in 0.13-μm PDSOI nMOSFETs with shallow trench isolation[J]. 中国物理B, 2018, 27(2): 28501-028501.
[4]	解鑫, 毕大伟, 胡志远, 朱慧龙, 张梦映, 张正选, 邹世昌. Influence of characteristics' measurement sequence on total ionizing dose effect in PDSOI nMOSFET[J]. 中国物理B, 2018, 27(12): 128501-128501.
[5]	郑齐文, 崔江维, 刘梦新, 苏丹丹, 周航, 马腾, 余学峰, 陆妩, 郭旗, 赵发展. Direct measurement and analysis of total ionizing dose effect on 130 nm PD SOI SRAM cell static noise margin[J]. 中国物理B, 2017, 26(9): 96103-096103.
[6]	樊双, 胡志远, 张正选, 宁冰旭, 毕大炜, 戴丽华, 张梦映, 张乐情. Total ionizing dose induced single transistor latchup in 130-nm PDSOI input/output NMOSFETs[J]. 中国物理B, 2017, 26(3): 36103-036103.
[7]	李威, 郑直, 汪志刚, 李平, 付晓君, 何峥嵘, 刘凡, 杨丰, 向凡, 刘伦才. A novel P-channel SOI LDMOS structure with non-depletion potential-clamped layer[J]. 中国物理B, 2017, 26(1): 17701-017701.
[8]	解冰清, 李博, 毕津顺, 卜建辉, 吴驰, 李彬鸿, 韩郑生, 罗家俊. Effect of cryogenic temperature characteristics on 0.18-μm silicon-on-insulator devices[J]. 中国物理B, 2016, 25(7): 78501-078501.
[9]	黄鹏程, 陈书明, 陈建军. Mechanism of floating body effect mitigation via cutting off source injection in a fully-depleted silicon-on-insulator technology[J]. 中国物理B, 2016, 25(3): 36103-036103.
[10]	王裕如, 刘祎鹤, 林兆江, 方冬, 李成州, 乔明, 张波. Modeling of a triple reduced surface field silicon-on-insulator lateral double-diffused metal-oxide-semiconductor field-effect transistor with low on-state resistance[J]. 中国物理B, 2016, 25(2): 27305-027305.
[11]	吕凯, 陈静, 黄瑜萍, 刘军, 罗杰馨, 王曦. Ultra-low temperature radio-frequency performance of partially depleted silicon-on-insulator n-type metal-oxide-semiconductor field-effect transistors with tunnel diode body contact structures[J]. 中国物理B, 2016, 25(11): 118503-118503.
[12]	吕凯, 陈静, 罗杰馨, 何伟伟, 黄建强, 柴展, 王曦. Effects of back gate bias on radio-frequency performance in partially depleted silicon-on-inslator nMOSFETs[J]. 中国物理B, 2015, 24(8): 88501-088501.
[13]	孙高迪, 董林玺, 薛忠营, 陈达, 郭庆磊, 母志强. Strain analysis of free-standing strained silicon-on-insulator nanomembrane[J]. , 2015, 24(3): 36801-036801.
[14]	刘力, 杨婷, 董建绩. Microwave photonic filter with a continuously tunable central frequency using an SOI high-Q microdisk resonator[J]. , 2014, 23(9): 93201-093201.
[15]	胡盛东, 武星河, 朱志, 金晶晶, 陈银晖. Partial-SOI high voltage laterally double-diffused MOS with a partially buried n⁺-layer[J]. 中国物理B, 2014, 23(6): 67101-067101.