中国物理B ›› 2008, Vol. 17 ›› Issue (12): 4599-4605.doi: 10.1088/1674-1056/17/12/044
赵发展1, 刘梦新1, 郭天雷1, 刘刚1, 海潮和1, 韩郑生1, 杨善潮2, 李瑞宾2, 林东生2, 陈伟2
Zhao Fa-Zhan (赵发展)a, Liu Meng-Xin (刘梦新)a, Guo Tian-Lei (郭天雷)a, Liu Gang (刘刚)a, Hai Chao-He (海潮和)a, Han Zheng-Sheng (韩郑生)a, Yang Shan-Chao (杨善潮)b, Li Rui-Bin (李瑞宾)b, Lin Dong-Sheng (林东生)b, Chen Wei (陈伟)b
摘要: This paper implements the study on the Dose Rate Upset effect of PDSOI SRAM (Partially Depleted Silicon-On-Insulator Static Random Access Memory) with the Qiangguang-I accelerator in Northwest Institute of Nuclear Technology. The SRAM (Static Random Access Memory) chips are developed by the Institute of Microelectronics of Chinese Academy of Sciences. It uses the full address test mode to determine the upset mechanisms. Specified address test is taken in the same time. The test results indicate that the upset threshold of the PDSOI SRAM is about 1x108Gy(Si)/s. However, there are few bits upset when the dose rate reaches up to 1.58x109Gy(Si)/s. The SRAM circuit can still work after the high level γ ray pulse. Finally, the upset mechanism is determined to be the rail span collapse by comparing the critical charge with the collected charge after γ ray pulse. The physical locations of upset cells are plotted in the layout of the SRAM to investigate the layout defect. Then, some layout optimizations have been taken to improve the dose rate hardened performance of the PDSOI SRAM.
中图分类号: (Pulse and digital circuits)