Modeling of trap-assisted tunneling on performance of charge trapping memory with consideration of trap position and energy level

doi:10.1088/1674-1056/25/8/088502

Abstract

In this work, the trap-assisted tunneling (TAT) mechanism is modeled as a two-step physical process for charge trapping memory (CTM). The influence of the TAT mechanism on CTM performance is investigated in consideration of various trap positions and energy levels. For the simulated CTM structure, simulation results indicate that the positions of oxide traps related to the maximum TAT current contribution shift towards the substrate interface and charge storage layer interface during time evolutions in programming and retention operations, respectively. Lower programming voltage and retention operations under higher temperature are found to be more sensitive to tunneling oxide degradation.

Keywords: trap assisted tunneling charge trapping memory tunneling oxide degradation

Received: 05 March 2016
Revised: 12 April 2016
Accepted manuscript online:

PACS:	85.30.De	(Semiconductor-device characterization, design, and modeling)
	85.30.-z	(Semiconductor devices)

Fund:

Project supported by the National Natural Science Foundation of China (Grant Nos. 61404005, 61421005, and 91434201).

Corresponding Authors: Gang Du
E-mail: gangdu@pku.edu.cn

Cite this article:

Zhi-Yuan Lun(伦志远), Yun Li(李云), Kai Zhao(赵凯), Gang Du(杜刚), Xiao-Yan Liu(刘晓彦), Yi Wang(王漪) Modeling of trap-assisted tunneling on performance of charge trapping memory with consideration of trap position and energy level 2016 Chin. Phys. B 25 088502

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Modeling of trap-assisted tunneling on performance of charge trapping memory with consideration of trap position and energy level

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