A statistical RCL interconnect delay model taking account of process variations

doi:10.1088/1674-1056/20/1/018401

Abstract As the feature size of the CMOS integrated circuit continues to shrink, process variations have become a key factor affecting the interconnect performance. Based on the equivalent Elmore model and the use of the polynomial chaos theory and the Galerkin method, we propose a linear statistical RCL interconnect delay model, taking into account process variations by successive application of the linear approximation method. Based on a variety of nano-CMOS process parameters, HSPICE simulation results show that the maximum error of the proposed model is less than 3.5%. The proposed model is simple, of high precision, and can be used in the analysis and design of nanometer integrated circuit interconnect systems.

Keywords: process variation interconnect line statistical delay successive linear approximation

Received: 30 March 2010
Revised: 23 August 2010
Accepted manuscript online:

PACS:	84.30.-r	(Electronic circuits)
	84.30.Bw

Fund: Project supported by the National Natural Science Foundation of China (Grant Nos. 60725415 and 60971066), the National Science & Technology Important Project of China (Grant No. 2009ZX01034-002-001-005), and The National Key Laboratory Foundation (Grant No. ZHD200904).

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Zhu Zhang-Ming(朱樟明), Wan Da-Jing(万达经), Yang Yin-Tang(杨银堂), and En Yun-Fei(恩云飞) A statistical RCL interconnect delay model taking account of process variations 2011 Chin. Phys. B 20 018401

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[1]	Statistical Elmore delay of RC interconnect tree Dong Gang(董刚), Yang Yang(杨杨), Chai Chang-Chun(柴常春), and Yang Yin-Tang(杨银堂). Chin. Phys. B, 2010, 19(11): 110202.

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A statistical RCL interconnect delay model taking account of process variations

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