Please wait a minute...
Chin. Phys. B, 2011, Vol. 20(1): 018401    DOI: 10.1088/1674-1056/20/1/018401
INTERDISCIPLINARY PHYSICS AND RELATED AREAS OF SCIENCE AND TECHNOLOGY Prev   Next  

A statistical RCL interconnect delay model taking account of process variations

Zhu Zhang-Ming(朱樟明), Wan Da-Jing(万达经), Yang Yin-Tang(杨银堂), and En Yun-Fei(恩云飞)
Microelectronics School, Xidian University, Xi'an 710071, China
Abstract  As the feature size of the CMOS integrated circuit continues to shrink, process variations have become a key factor affecting the interconnect performance. Based on the equivalent Elmore model and the use of the polynomial chaos theory and the Galerkin method, we propose a linear statistical RCL interconnect delay model, taking into account process variations by successive application of the linear approximation method. Based on a variety of nano-CMOS process parameters, HSPICE simulation results show that the maximum error of the proposed model is less than 3.5%. The proposed model is simple, of high precision, and can be used in the analysis and design of nanometer integrated circuit interconnect systems.
Keywords:  process variation      interconnect line      statistical delay      successive linear approximation  
Received:  30 March 2010      Revised:  23 August 2010      Accepted manuscript online: 
PACS:  84.30.-r (Electronic circuits)  
  84.30.Bw  
Fund: Project supported by the National Natural Science Foundation of China (Grant Nos. 60725415 and 60971066), the National Science & Technology Important Project of China (Grant No. 2009ZX01034-002-001-005), and The National Key Laboratory Foundation (Grant No. ZHD200904).

Cite this article: 

Zhu Zhang-Ming(朱樟明), Wan Da-Jing(万达经), Yang Yin-Tang(杨银堂), and En Yun-Fei(恩云飞) A statistical RCL interconnect delay model taking account of process variations 2011 Chin. Phys. B 20 018401

[1] Li B, Peh L S and Patra P 2008 IEEE International Symposium on Networks-on-Chip (UK: Newcastle University) p125
[2] Lin Y and He L 2008 IEEE Transaction on Very Large Scale Integration System 16 141
[3] Sun P and Luo R 2009 Proceedings of the 11th International Workshop on System Level Interconnect Prediction (USA: San Francisco) p19
[4] Raghuandan C, Sainarayanan K S and Srinivas M B 2008 Proceedings of the 9th International Symposium on Quality Electronic Design (ISQED) (USA: San Jose) p43
[5] Kim S Y and Wong S S 2007 IEEE Trans. On Circuits and System I: Reg. Papers 54 2001
[6] Zhou G, Su L and Jin D 2008 IEEE 13th Asia and South Pacific Design Automation Conference (Korea: Soul) p510
[7] Zarrabi H, Al-Khalili A J and Savaria Y 2009 Proceedings of the 19th ACM Great Lakes Symposium on VLSI (USA: New York) p45
[8] Elmore W C 1948 J. Appl. Phys. 19 55
[9] Ismail Y I, Friedman E G and Neves J L 2000 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 19 83
[10] Dai W and Hao J 2001 IEEE International Workshop on Statistical Methodology (Japan: Kyoto) p51
[11] Ghanem R G and Spanos P 2003 Stochastic Finite Elements: A Spectral Approach (New York: Spinger)
[12] Wang J, Ghanta P and Vrudhula S 2004 Intl. Conf. on Computer-Aided Design (USA: San Jose) p880
[13] Agarwal K, Agarwal M and Sylvester D 2006 IEEE Trans. on Computer Aided Design of Integrated Circuits and Systems 25 1273
[14] Wong S C, Lee G Y and Ma D J 2000 IEEE Transactions on Semiconductor Manufacturing 13 108
[15] Qi X N, Wang G F and Yu Z P 2000 IEEE Custom Integrated Circuits Conference (Florida, USA: Orlando) p487
[16] Semiconductor Industry Association 2007 International Technology Roadmap for Semiconductors endfootnotesize
[1] Statistical Elmore delay of RC interconnect tree
Dong Gang(董刚), Yang Yang(杨杨), Chai Chang-Chun(柴常春), and Yang Yin-Tang(杨银堂). Chin. Phys. B, 2010, 19(11): 110202.
No Suggested Reading articles found!