中国物理B ›› 2010, Vol. 19 ›› Issue (5): 57302-057302.doi: 10.1088/1674-1056/19/5/057302

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Comparative studies of Ge and Si p-channel metal-oxide-semiconductor field-effect-transistors with HfSiON dielectric and TaN metal gate

胡爱斌, 徐秋霞   

  1. Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China
  • 收稿日期:2009-10-18 修回日期:2009-11-09 出版日期:2010-05-15 发布日期:2010-05-15
  • 基金资助:
    Project supported by the National Basic Research Program of China (Grant No.~2006CB302704).

Comparative studies of Ge and Si p-channel metal-oxide-semiconductor field-effect-transistors with HfSiON dielectric and TaN metal gate

Hu Ai-Bin(胡爱斌) and Xu Qiu-Xia(徐秋霞)   

  1. Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China
  • Received:2009-10-18 Revised:2009-11-09 Online:2010-05-15 Published:2010-05-15
  • Supported by:
    Project supported by the National Basic Research Program of China (Grant No.~2006CB302704).

摘要: Ge and Si p-channel metal--oxide--semiconductor field-effect-transistors (p-MOSFETs) with hafnium silicon oxynitride (HfSiON) gate dielectric and tantalum nitride (TaN) metal gate are fabricated. Self-isolated ring-type transistor structures with two masks are employed. W/TaN metal stacks are used as gate electrode and shadow masks of source/drain implantation separately. Capacitance--voltage curve hysteresis of Ge metal--oxide--semiconductor (MOS) capacitors may be caused by charge trapping centres in GeO$_{x}$ ($1

Abstract: Ge and Si p-channel metal--oxide--semiconductor field-effect-transistors (p-MOSFETs) with hafnium silicon oxynitride (HfSiON) gate dielectric and tantalum nitride (TaN) metal gate are fabricated. Self-isolated ring-type transistor structures with two masks are employed. W/TaN metal stacks are used as gate electrode and shadow masks of source/drain implantation separately. Capacitance--voltage curve hysteresis of Ge metal--oxide--semiconductor (MOS) capacitors may be caused by charge trapping centres in GeO$_{x}$ (1 < $x$ < 2).  Effective hole mobilities of Ge and Si transistors are extracted by using a channel conductance method. The peak hole mobilities of Si and Ge transistors are 33.4 cm2/(V$\cdot$s) and 81.0 cm2/(V$\cdot$s), respectively. Ge transistor has a hole mobility 2.4 times higher than that of Si control sample. 

Key words: Ge substrate, transistor, HfSiON, hole mobility

中图分类号:  (Field effect devices)

  • 85.30.Tv
85.30.De (Semiconductor-device characterization, design, and modeling) 85.40.Hp (Lithography, masks and pattern transfer)