中国物理B ›› 2023, Vol. 32 ›› Issue (3): 38501-038501.doi: 10.1088/1674-1056/ac873d

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High performance carrier stored trench bipolar transistor with dual shielding structure

Jin-Ping Zhang(张金平)1,2,†, Hao-Nan Deng(邓浩楠)1, Rong-Rong Zhu(朱镕镕)1, Ze-Hong Li(李泽宏)1, and Bo Zhang(张波)1   

  1. 1 State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China(UESTC), Chengdu 610054, China;
    2 Institute of Electronic and Information Engineering of UESTC in Guangdong, Dongguan 523808, China
  • 收稿日期:2022-06-24 修回日期:2022-07-23 接受日期:2022-08-05 出版日期:2023-02-14 发布日期:2023-02-14
  • 通讯作者: Jin-Ping Zhang E-mail:jinpingzhang@uestc.edu.cn
  • 基金资助:
    Project supported by the National Key Research and Development Program of China (Grant No. 2018YFB1201802), the Key Realm R&D Program of Guangdong Province, China (Grant No. 2018B010142001), and the Guangdong Basic and Applied Basic Research Foundation, China (Grant No. 2020A1515010128).

High performance carrier stored trench bipolar transistor with dual shielding structure

Jin-Ping Zhang(张金平)1,2,†, Hao-Nan Deng(邓浩楠)1, Rong-Rong Zhu(朱镕镕)1, Ze-Hong Li(李泽宏)1, and Bo Zhang(张波)1   

  1. 1 State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China(UESTC), Chengdu 610054, China;
    2 Institute of Electronic and Information Engineering of UESTC in Guangdong, Dongguan 523808, China
  • Received:2022-06-24 Revised:2022-07-23 Accepted:2022-08-05 Online:2023-02-14 Published:2023-02-14
  • Contact: Jin-Ping Zhang E-mail:jinpingzhang@uestc.edu.cn
  • Supported by:
    Project supported by the National Key Research and Development Program of China (Grant No. 2018YFB1201802), the Key Realm R&D Program of Guangdong Province, China (Grant No. 2018B010142001), and the Guangdong Basic and Applied Basic Research Foundation, China (Grant No. 2020A1515010128).

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摘要： We propose a novel high performance carrier stored trench bipolar transistor (CSTBT) with dual shielding structure (DSS-CSTBT). The proposed DSS-CSTBT features a double trench structure with different trench profiles in the surface, in which a shallow gate trench is shielded by a deep emitter trench and a thick oxide layer under it. Compared with the conventional CSTBT (con-CSTBT), the proposed DSS-CSTBT not only alleviates the negative impact of the shallow gate trench and highly doped CS layer on the breakdown voltage (BV), but also well reduces the gate-collector capacitance $C_{\rm GC}$, gate charge $Q_{\rm G}$, and turn-off loss $E_{\rm OFF}$ of the device. Furthermore, lower turn-on loss $E_{\rm ON}$ and gate drive loss $E_{\rm DR}$ are also obtained. Simulation results show that with the same CS layer doping concentration $N_{\rm CS}=1.5\times10^{16 }$ cm$^{-3}$, the BV increases from 1312 V of the con-CSTBT to 1423 V of the proposed DSS-CSTBT with oxide layer thickness under gate ($T_{\rm og2}$) of 1 μm. Moreover, compared with the con-CSTBT, the $C_{\rm GC}$ at $V_{\rm CE} $ of 25 V and miller plateau charge ($Q_{\rm GC}$) for the proposed DSS-CSTBT with $T_{\rm og2}$ of 1 μm are reduced by 79.4% and 74.3%, respectively. With the $V_{\rm GE} $ increases from 0 V to 15 V, the total $Q_{\rm G}$ for the proposed DSS-CSTBT with $T_{\rm og2}$ of 1 μm is reduced by 49.5%. As a result, at the same on-state voltage drop ($V_{\rm CEON}$) of 1.55 V, the $E_{\rm ON}$ and $E_{\rm OFF}$ are reduced from 20.3 mJ/cm$^{2}$ and 19.3 mJ/cm$^{2}$ for the con-CSTBT to 8.2 mJ/cm$^{2}$ and 9.7 mJ/cm$^{2}$ for the proposed DSS-CSTBT with $T_{\rm og2}$ of 1 μm, respectively. The proposed DSS-CSTBT not only significantly improves the trade-off relationship between the $V_{\rm CEON}$ and $E_{\rm OFF }$ but also greatly reduces the $E_{\rm ON}$.

关键词: carrier stored trench bipolar transistor (CSTBT), dual shielding structure, gate-collector capacitance, power loss

Abstract: We propose a novel high performance carrier stored trench bipolar transistor (CSTBT) with dual shielding structure (DSS-CSTBT). The proposed DSS-CSTBT features a double trench structure with different trench profiles in the surface, in which a shallow gate trench is shielded by a deep emitter trench and a thick oxide layer under it. Compared with the conventional CSTBT (con-CSTBT), the proposed DSS-CSTBT not only alleviates the negative impact of the shallow gate trench and highly doped CS layer on the breakdown voltage (BV), but also well reduces the gate-collector capacitance $C_{\rm GC}$, gate charge $Q_{\rm G}$, and turn-off loss $E_{\rm OFF}$ of the device. Furthermore, lower turn-on loss $E_{\rm ON}$ and gate drive loss $E_{\rm DR}$ are also obtained. Simulation results show that with the same CS layer doping concentration $N_{\rm CS}=1.5\times10^{16 }$ cm$^{-3}$, the BV increases from 1312 V of the con-CSTBT to 1423 V of the proposed DSS-CSTBT with oxide layer thickness under gate ($T_{\rm og2}$) of 1 μm. Moreover, compared with the con-CSTBT, the $C_{\rm GC}$ at $V_{\rm CE} $ of 25 V and miller plateau charge ($Q_{\rm GC}$) for the proposed DSS-CSTBT with $T_{\rm og2}$ of 1 μm are reduced by 79.4% and 74.3%, respectively. With the $V_{\rm GE} $ increases from 0 V to 15 V, the total $Q_{\rm G}$ for the proposed DSS-CSTBT with $T_{\rm og2}$ of 1 μm is reduced by 49.5%. As a result, at the same on-state voltage drop ($V_{\rm CEON}$) of 1.55 V, the $E_{\rm ON}$ and $E_{\rm OFF}$ are reduced from 20.3 mJ/cm$^{2}$ and 19.3 mJ/cm$^{2}$ for the con-CSTBT to 8.2 mJ/cm$^{2}$ and 9.7 mJ/cm$^{2}$ for the proposed DSS-CSTBT with $T_{\rm og2}$ of 1 μm, respectively. The proposed DSS-CSTBT not only significantly improves the trade-off relationship between the $V_{\rm CEON}$ and $E_{\rm OFF }$ but also greatly reduces the $E_{\rm ON}$.

Key words: carrier stored trench bipolar transistor (CSTBT), dual shielding structure, gate-collector capacitance, power loss

中图分类号:  (Semiconductor-device characterization, design, and modeling)

  • 85.30.De
85.30.Pq (Bipolar transistors) 85.30.Tv (Field effect devices)