A multilevel nano-scale interconnection RLC delay model

doi:10.1088/1674-1056/19/7/077802

中国物理B ›› 2010, Vol. 19 ›› Issue (7): 77802-077802.doi: 10.1088/1674-1056/19/7/077802

A multilevel nano-scale interconnection RLC delay model

朱樟明, 修利平, 杨银堂

Microelectronics School, Xidian University, Xi'an 710071, China

出版日期:2010-07-15 发布日期:2010-07-15
基金资助:
Project supported by the National Natural Science Foundation of China (Grant Nos. 60971066 and 60725415), the National High-Tech Program of China (Grant Nos. 2009AA01Z258 and 2009AA01Z260) and National Key Laboratory Foundation of China (Grant No. ZHD200904).

A multilevel nano-scale interconnection RLC delay model

Zhu Zhang-Ming (朱樟明), Xiu Li-Ping (修利平), Yang Yin-Tang (杨银堂)

Microelectronics School, Xidian University, Xi'an 710071, China

Online:2010-07-15 Published:2010-07-15
Supported by:
Project supported by the National Natural Science Foundation of China (Grant Nos. 60971066 and 60725415), the National High-Tech Program of China (Grant Nos. 2009AA01Z258 and 2009AA01Z260) and National Key Laboratory Foundation of China (Grant No. ZHD200904).

摘要/Abstract

摘要： Based on the multilevel interconnections temperature distribution model and the RLC interconnection delay model of the integrate circuit, this paper proposes a multilevel nano-scale interconnection RLC delay model with the method of numerical analysis, the proposed analytical model has summed up the influence of the configuration of multilevel interconnections, the via heat transfer and self-heating effect on the interconnection delay, which is closer to the actual situation. Delay simulation results show that the proposed model has high precision within 5% errors for global interconnections based on the 65 nm CMOS interconnection and material parameter, which can be applied in nanometer CMOS system chip computer-aided design.

Abstract: Based on the multilevel interconnections temperature distribution model and the RLC interconnection delay model of the integrate circuit, this paper proposes a multilevel nano-scale interconnection RLC delay model with the method of numerical analysis, the proposed analytical model has summed up the influence of the configuration of multilevel interconnections, the via heat transfer and self-heating effect on the interconnection delay, which is closer to the actual situation. Delay simulation results show that the proposed model has high precision within 5% errors for global interconnections based on the 65 nm CMOS interconnection and material parameter, which can be applied in nanometer CMOS system chip computer-aided design.

Key words: multilevel interconnection, thermal distribution, RLC interconnection delay, current density

中图分类号: (Computer-aided design of microcircuits; layout and modeling)

85.40.Bh

84.30.Bv (Circuit theory)

朱樟明, 修利平, 杨银堂. A multilevel nano-scale interconnection RLC delay model[J]. 中国物理B, 2010, 19(7): 77802-077802.

Zhu Zhang-Ming (朱樟明), Xiu Li-Ping (修利平), Yang Yin-Tang (杨银堂). A multilevel nano-scale interconnection RLC delay model[J]. Chin. Phys. B, 2010, 19(7): 77802-077802.

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A multilevel nano-scale interconnection RLC delay model

A multilevel nano-scale interconnection RLC delay model

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