中国物理B ›› 2009, Vol. 18 ›› Issue (11): 4995-5000.doi: 10.1088/1674-1056/18/11/063

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A novel analytical thermal model for multilevel nano-scale interconnects considering the via effect

朱樟明, 李儒, 郝报田, 杨银堂   

  1. Microelectronics Institute, Xidian University, Xi'an 710071, China
  • 收稿日期:2009-05-18 修回日期:2009-06-25 出版日期:2009-11-20 发布日期:2009-11-20
  • 基金资助:
    Project supported by the National Natural Science Foundation of China (Grant Nos 60676009 and 60725415), the National High Technology Research and Development Program of China (Grant Nos 2009AA01Z258 and 2009AA01Z260).

A novel analytical thermal model for multilevel nano-scale interconnects considering the via effect

Zhu Zhang-Ming(朱樟明)†,Li Ru(李儒), Hao Bao-Tian(郝报田), and Yang Yin-Tang(杨银堂)   

  1. Microelectronics Institute, Xidian University, Xi'an 710071, China
  • Received:2009-05-18 Revised:2009-06-25 Online:2009-11-20 Published:2009-11-20
  • Supported by:
    Project supported by the National Natural Science Foundation of China (Grant Nos 60676009 and 60725415), the National High Technology Research and Development Program of China (Grant Nos 2009AA01Z258 and 2009AA01Z260).

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摘要： Based on the heat diffusion equation of multilevel interconnects, a novel analytical thermal model for multilevel nano-scale interconnects considering the via effect is presented, which can compute quickly the temperature of multilevel interconnects, with substrate temperature given. Based on the proposed model and the 65~nm complementary metal oxide semiconductor (CMOS) process parameter, the temperature of nano-scale interconnects is computed. The computed results show that the via effect has a great effect on local interconnects, but the reduction of thermal conductivity has little effect on local interconnects. With the reduction of thermal conductivity or the increase of current density, however, the temperature of global interconnects rises greatly, which can result in a great deterioration in their performance. The proposed model can be applied to computer aided design (CAD) of very large-scale integrated circuits (VLSIs) in nano-scale technologies.

Abstract: Based on the heat diffusion equation of multilevel interconnects, a novel analytical thermal model for multilevel nano-scale interconnects considering the via effect is presented, which can compute quickly the temperature of multilevel interconnects, with substrate temperature given. Based on the proposed model and the 65 nm complementary metal oxide semiconductor (CMOS) process parameter, the temperature of nano-scale interconnects is computed. The computed results show that the via effect has a great effect on local interconnects, but the reduction of thermal conductivity has little effect on local interconnects. With the reduction of thermal conductivity or the increase of current density, however, the temperature of global interconnects rises greatly, which can result in a great deterioration in their performance. The proposed model can be applied to computer aided design (CAD) of very large-scale integrated circuits (VLSIs) in nano-scale technologies.

Key words: multilevel interconnects, temperature distribution, self-heating, via effect

中图分类号:  (Computer-aided design of microcircuits; layout and modeling)

  • 85.40.Bh
85.40.Ry (Impurity doping, diffusion and ion implantation technology) 66.70.-f (Nonelectronic thermal conduction and heat-pulse propagation in solids;thermal waves)