中国物理B ›› 2009, Vol. 18 ›› Issue (3): 1188-1193.doi: 10.1088/1674-1056/18/3/058

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A novel interconnect-optimal repeater insertion model with target delay constraint in 65nm CMOS

杨银堂1, 朱樟明2, 钱利波2   

  1. (1)Institute of Microelectronics, Xidian University, Xi'an 710071, China; (2)Institute of Microelectronics, Xidian University, Xi'an 710071, China
  • 收稿日期:2008-06-17 修回日期:2008-09-04 出版日期:2009-03-20 发布日期:2009-03-20
  • 基金资助:
    Project supported by the National Natural Science Foundation of the China (Grant Nos 60676009 and 60776034), the Doctor Foundation of Ministry of Education of China (Grant No 20050701015), and the National Outstanding Young Scientist Foundation of China

A novel interconnect-optimal repeater insertion model with target delay constraint in 65nm CMOS

Zhu Zhang-Ming(朱樟明), Qian Li-Bo(钱利波), and Yang Yin-Tang(杨银堂)   

  1. Institute of Microelectronics, Xidian University, Xi'an 710071, China
  • Received:2008-06-17 Revised:2008-09-04 Online:2009-03-20 Published:2009-03-20
  • Supported by:
    Project supported by the National Natural Science Foundation of the China (Grant Nos 60676009 and 60776034), the Doctor Foundation of Ministry of Education of China (Grant No 20050701015), and the National Outstanding Young Scientist Foundation of China

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摘要： Repeater optimization is the key for SOC (System on Chip) interconnect delay design. This paper proposes a novel optimal model for minimizing power and area overhead of repeaters while meeting the target performance of on-chip interconnect lines. It also presents Lagrangian function to find the number of repeaters and their sizes required for minimizing area and power overhead with target delay constraint. Based on the 65 nanometre CMOS technology, the computed results of the intermediate and global lines show that the proposed model can significantly reduce area and power of interconnected lines, and the better performance will be achieved with the longer line. The results compared with the reference paper demonstrate the validity of this model. It can be integrated into repeater design methodology and CAD (computer aided design) tool for interconnect planning in nanometre SOC.

关键词: distributed RLC, interconnect power dissipation and area, target delay, lagrangian function

Abstract: Repeater optimization is the key for SOC (System on Chip) interconnect delay design. This paper proposes a novel optimal model for minimizing power and area overhead of repeaters while meeting the target performance of on-chip interconnect lines. It also presents Lagrangian function to find the number of repeaters and their sizes required for minimizing area and power overhead with target delay constraint. Based on the 65 nanometre CMOS technology, the computed results of the intermediate and global lines show that the proposed model can significantly reduce area and power of interconnected lines, and the better performance will be achieved with the longer line. The results compared with the reference paper demonstrate the validity of this model. It can be integrated into repeater design methodology and CAD (computer aided design) tool for interconnect planning in nanometre SOC.

Key words: distributed RLC, interconnect power dissipation and area, target delay, lagrangian function

中图分类号:  (Metallization, contacts, interconnects; device isolation)

  • 85.40.Ls
85.40.Bh (Computer-aided design of microcircuits; layout and modeling) 85.35.-p (Nanoelectronic devices) 85.30.Tv (Field effect devices)