† Corresponding author. E-mail:

Project supported by the Research Program of the National University of Defense Technology (Grant No. JC 13-06-04).

In this paper, the three-dimensional (3D) coupling effect is discussed for nanowire junctionless silicon-on-insulator (SOI) FinFETs. With fin width decreasing from 100 nm to 7 nm, the electric field induced by the lateral gates increases and therefore the influence of back gate on the threshold voltage weakens. For a narrow and tall fin, the lateral gates mainly control the channel and therefore the effect of back gate decreases. A simple two-dimensional (2D) potential model is proposed for the subthreshold region of junctionless SOI FinFET. TCAD simulations validate our model. It can be used to extract the threshold voltage and doping concentration. In addition, the tuning of back gate on the threshold voltage can be predicted.

Since their invention by J-P. Colinge, junctionless (JL) transistors have been a compelling candidate for ultra-scaled devices due to their excellent electrostatic gate control and simplified junction engineering.^{[1]} These transistors have shown the promising applications in the field of analog/RF,^{[2]} logic^{[3]} and sensing circuits.^{[4]} JL MOSFETs are usually designed with heavily doped silicon films (∼ 10^{19} cm^{−3}) in order to achieve enough drain current. Owing to the high doping concentration of the channel, the carrier transport in a JL transistor relies on volume conduction instead of the conventional surface inversion in MOSFET. This device is switched off by fully depleting its heavily doped channel. Thus, the geometry of the channel must be small enough to permit the full depletion at a desired gate voltage. The junctionless transistor can operate in three modes: full depletion, partial depletion, and surface accumulation. The threshold voltage and flat-band voltage are the key identifiers to distinguish the three modes.

In classical inversion-mode FD SOI MOSFET, the operation of the transistor is governed by both front and back channels. This phenomenon is well known as the coupling effect between front and back gates, which has been demonstrated to have a strong influence on the threshold voltage and mobility.^{[5–7]} However, most studies of the coupling effect involve the inversion-mode SOI MOSFETs with undoped or low-doped channel. There are few reports on the coupling effect in the JL transistor with a heavily doped channel. Owing to the small cross-section of the channel in the JL transistor, the coupling effect is expected to happen as in the inversion-mode SOI MOSFETs.^{[8,9]}

On the other hand, the junctionless SOI FinFET with multiple gates has been fabricated due to its novel performance.^{[10,11]} In the JL SOI FinFET, we must consider the effect of the lateral electric field between the two lateral gates. This lateral electric field which makes the difference between planar and FinFETs enhances the coupling effect. The enhanced coupling effect will lead to the difficulties in determining the threshold voltage, which reflects the full depletion of the doped channel. Several models based on the approximate solution of the Poisson equation have been proposed: a one-dimensional (1D) model for double-gate JL devices,^{[12–14]} a 1D potential model in the full depletion region for double-gate JL transistors,^{[15]} a 2D surface-potential-based current model for triple-gate transistors,^{[16]} etc. While 2D models are too complicated to be used for parameter extraction, a 1D model does not consider the coupling effect between the gates.^{[17]} Therefore, a simple model including the coupling effect between gates is imperative for parameter extraction in JL SOI FinFET.

In this paper, we will take the coupling effect into account in the modeling of JL SOI FinFET. We focus on the modeling of potential and the coupling effect in the subthreshold region (depletion region for JL transistor). Section 2 will show the evidence of coupling effects in JL SOI FinFETs. In Section 3, we will propose a 2D model for potential distribution in a subthreshold region. TCAD simulations are performed to validate our model. Based on this model, a simple and fast method to determine the threshold voltage is developed by considering the coupling effects, which will be explained in Section 4. In Section 5 we will draw some conclusions from the present study.

Before the 2D analytical model with considering the coupling effect in JL SOI FinFETs, we will firstly show the simulated characteristics of JL SOI FinFETs. The coupling effects will be uncovered by comparing the influences of fin width, film thickness and backgate on the characteristic curves.

Figure ^{[18]} The thickness values of gate oxide and buried oxide (BOX) are respectively 1.2 nm and 145 nm.^{[18]} The channel has a high arsenic doping concentration of ∼ 10^{19} cm^{−3}.^{[18]} In order to reduce the access resistance, the source and drain are heavily doped with arsenic (10^{20} cm^{−3}). The back gate contact is directly placed on the bottom of buried oxide in order to omit the effect of substrate depletion. The gate length is fixed to be 200 nm to avoid the short-channel effect. The width of channel varies from 7 nm to 100 nm.

Synopsys Sentaurus TCAD is employed for all simulations.^{[19]} Fermi-Dirac distribution is employed due to the heavily doped channel. The effect of doping, velocity saturation and the surface scattering are considered. The Shockley–Read–Hall recombination dependent on the doping level and Auger recombination are also included. The work-functions of the front and back gates are selected to make the flat-band voltages (*V*_{FBF} and *V*_{FBB}) equal zero. Both the front- and the back-gate leakages are neglected.^{[18]} The drain is 0.05 V and the gate is swept from −1.5 V to +1.5 V. All the simulations are 3D simulations.

Figure *V*_{FG}) for JL SOI FinFETs with different fin widths. For *V*_{FG} = 0 V (corresponding to flat-band), the drain current is significant due to volume conduction. At a higher front gate voltage, the drain current increases further as a result of an activated accumulation channel under the front gate. For *V*_{FG} < 0 V, the current decreases until the channel is fully depleted (∼ −1.1 V for *W*_{fin} = 100 nm, where a sharp decrease of drain current is observed in the semi-logarithmic scale of Fig.

These modes of operation are also reflected by the contours of electron density in Fig. *V*_{FG} = *V*_{FBF} (input value is 0 V), the drain current equals the volume current (Fig.

accumulation mode (*V*_{FG} > *V*_{FBF}), in which the drain current is the sum of volume current and accumulation current (Fig.

partial depletion mode, in which the drain current comes from the volume conduction in the undepleted region (Fig.

full depletion mode, in which the drain current decreases sharply with *V*_{FG} (Fig.

The effect of fin width on the transconductance curves *g*_{m}(*V*_{FG}) is shown in Fig. *W*_{fin} = 100 nm), a plateau appears in the partially depleted region (−1.1 V < *V*_{FG} < 0 V) due to the volume conduction. With the fin width decreasing, the *g*_{m} plateau reduces until it disappears. This can be attributed to the enhanced control of lateral gates for narrower device. The effect of film thickness is also simulated as shown in Fig. *W*_{fin} = 9 nm), *g*_{m} shifts negatively with increasing film thickness due to the reduced control of the top gate. The transconductance and current are obviously stronger if one dimension of the fin (width or thickness) increases. The other dimension should be small enough to guarantee device turn-off.

Figure *V*_{BG} < 0 V, the back channel is simply depleted (strong inversion would be obtained for *V*_{BG} < −80 V according to Ref. [20]), and therefore the drain current decreases. For narrow JL SOI FinFET, the effect of back gate on the drain current weakens due to the domination of lateral gates as shown in Fig.

This suppression of coupling effect between top and back gates is also visible in the comparison among *g*_{m}(*V*_{FG}) curves under different back gate biases (Fig. *g*_{m} strongly varies with *V*_{BG} only in the partial depletion mode (*V*_{FG} < −0.3 V), but almost keeps unchanged in the accumulation mode (*V*_{FG} > 0 V); for narrow JL FinFET, the variation of *g*_{m} with *V*_{BG} reduces. This is similar to the effect of fin width on the coupling effect between top and back gates reported in inversion-mode SOI FinFETs.^{[9]} For a narrow and tall JL SOI FinFET, the lateral gates completely control the channel and therefore the coupling between top and back gate has a smaller effect as shown in Fig.

In summary, the coupling effect in JL SOI FinFET plays the same role as in the inversion-mode vertical DG SOI FinFET^{[9]}

In the 2D analytical model of triple-gate SOI FinFETs proposed by Akarvardar *et al.*,^{[22]} a parabolic potential variation between the two lateral gates is assumed. Here, we still assume that the potential profile between the two lateral gates is parabolic in the JL SOI FinFETs:

*φ*(

*x*,

*y*) is the 2D body potential in heavily doped body.

The coefficients of Eq. (

*V*

_{FBF}is the flat band voltage for the front gate,

*ɛ*

_{si}is the silicon permittivity,

*C*

_{ox}is the capacitance per unit area for the oxide of the front gate, and

*W*

_{fin}is the width of the fin. The two lateral gates are identical, so are the surface potentials:

*φ*(−

*W*

_{fin}/2,

*y*) =

*φ*(

*W*

_{fin}/2,y) =

*φ*

_{sf}. Assume that corner effects, quantum-mechanical effects, substrate depletion (under the BOX) and drain bias effect can be ignored.

^{[10,11,21]}Using Eqs. (

*η*

_{0}is actually equal to the ratio between

*C*

_{fin}and

*C*

_{ox}.

*C*

_{fin}=

*ɛ*

_{si}/

*W*

_{fin}is the “lateral” channel capacitance per unit area, defined in the 2D model of triple-gate SOI FinFETs.

^{[22]}Therefore, equation (

^{19}cm

^{−3}). Therefore, the fixed charge cannot be neglected in the full depletion region. Thus, the 2D Poisson equation for an n-channel junctionless FinFET is given by

*x*= 0, equation (

*C*

_{3}and

*C*

_{4}are the coefficients determined by the boundary conditions of the top (

*y*= −

*T*

_{si}/2) and bottom (

*y*=

*T*

_{si}/2) interfaces. Note that the thickness of the top gate oxide is equal to that of the lateral gate oxide in the modeled triple gate JL transistor.

*V*

_{FBB}is the flat-band voltage for back channel,

*C*

_{BOX}and

*C*

_{tox}are respectively the capacitance per unit area for BOX and the oxide of the top gate.

Substituting Eq. (*C*_{3} and *C*_{4} as

*W*

_{0}represents the equivalent fin width when the channel is controlled by top and back gates (

*η*

_{0}=

*ɛ*

_{si}/

*C*

_{ox}

*W*

_{fin}=

*C*

_{fin}/

*C*

_{ox}and

In order to validate our model for the potential distribution in JL SOI FinFET, we make a comparison of *φ*(0,*y*), the potential of the full depletion region along *x* = 0 (vertically cut in the middle of the channel, see Fig.

However, in the partial depletion region, the modeled potentials deviate from the simulated ones as shown in Fig.

The effects of back gate on the potential in both wide and narrow JL SOI FinFETs are shown in Fig. *V*_{FG} < −1 V) is needed to obtain full depletion. When the channel at the bottom is depleted (*V*_{BG} = − 10 & −20 V), the modeled potentials (circles and squares in Fig. *y* = 4.5 nm) as shown in Fig.

In summary, this 2D potential model works in the full depletion regime with zero back gate bias or with *V*_{BG} < 0 V (depletion at back interface).

Since our 2D potential model successfully applies to the full depletion region of nano-channel JL SOI FinFET, we can use it to extract the threshold voltage, which is a key identifier to distinguish the full and partial depletion regions. Before using the model, we will introduce the current-voltage method proposed by Jeon *et al.*^{[23]} to extract threshold voltage.

In a planar junctionless transistor, the threshold voltage is determined from the derivative of the transconductance (d*g*_{m}/d*V*_{FG}), shown in Fig. ^{[23]} The first peak *P*_{1} corresponds to flat-band voltage, where the channel of the junctionless transistor just changes from surface accumulation to neutral state; the second peak *P*_{2} exhibits the threshold voltage, separating the partial region from the full depletion region (dotted line in Fig. *P*_{2},^{[23]} also making the threshold voltage extraction impossible.

According to Ref. [15], the threshold voltage *V*_{THF} for a junctionless transistor can be defined as the front gate voltage when the channel is just fully depleted. It is given as the maximum potential at (*x*, *y*) = (0, −*T*_{si}/2) for *V*_{BG} = 0 V from Eq. (

*V*

_{FBF}= 0 V) as shown in Fig.

*g*

_{m}/d

*V*

_{FG}(Fig.

^{[23]}The deviation for wide fin (

*W*

_{fin}> 30 nm) can possibly be attributed to the effect of mobile charge. With a wider fin, the mobile charge density is larger for

*V*

_{FG}=

*V*

_{THF}, leading to the imperfection of full depletion approximation (see the large subthreshold current for wide JL in Fig.

For depletion in the back channel, the point *y*_{m} depleted finally lies in the middle of the channel along *x* = 0. Assume that the potential at *y*_{m} does not vary with *V*_{FG} nor *V*_{BG} and is always equal to the Fermi potential *φ*_{F}, we have

*V*

_{FG}=

*V*

_{THF}, the electric field at

*y*

_{m}approximates to zero:

*y*

_{m}and

*V*

_{BG}as shown in Fig.

*V*

_{BG},

*y*

_{m}shifts from the bottom of the fin toward the top. For a narrower fin, stronger depletion is induced by lateral gates and therefore this shift is larger. The threshold voltage is modeled as

*g*

_{m}/d

*V*

_{FG}method and Eq. (

*V*

_{BG}. Our model shows good agreement in particular for nanowires. For a wide fin, the threshold voltage increases more negatively, which can be explained by the fact that the back gate helps to deplete the channel. For a narrower fin, the channel is mainly controlled by lateral gates and therefore the variation of threshold voltage is smaller.

It follows that equation (*V*_{BG} = 0 V or depletion at the back interface, if the flat-band voltages for front and back gates and the doping concentrations are known from technology.

Once the threshold voltage and flat-band voltage are known, the doping concentration of the channel can be determined. We can rewrite Eq. (

^{19}cm

^{−3}) for

*W*

_{fin}> 10 nm. For narrower JL FinFETs (

*W*

_{fin}< 10 nm), the extracted doping levels are a little underestimated. This can possibly be explained by the enhanced corner effects.

In this paper, we prove the coupling effects for JL SOI FinFETs and propose a simple analytical model to determine the 2D potential profile within the body. The very good agreement obtained between simulated and modeling results validates the model. It works well in the full depletion region. The proposed models can be used for analysis of the coupling effect, characterization and optimization of geometry in any other heavily doped FinFETs. On the other hand, understanding these coupling effects and modeling them accurately are of great importance for applications. For example, increasing threshold voltage can reduce leakage current and power consumption. Conversely, lower operating bias is achieved with reduced threshold voltage. Also, we can co-integrate different functions into the same chip by tuning the threshold voltage.

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