An analytical model for nanowire junctionless SOI FinFETs with considering three-dimensional coupling effect

Liu Fan-Yu^{1, †,}, Liu Heng-Zhu¹, Liu Bi-Wei¹, Guo Yu-Feng²

(a) Plots of simulated dg_m/dV_FG versus V_FG for different values of fin width W_fin, and (b) plots of threshold voltage of front gate extracted from Eq. (14) and the second peak of dg_m/dV_FG, versus. fin width.