Abstract: The influences of reducing the supply voltage on single event upset (SEU) and multiple-cell upset (MCU) in two kinds of 65-nm static random access memories (SRAMs) are characterized across a wide linear energy transfer (LET) range. The results show that the influence of the voltage variation on SEU cross section clearly depends on the LET value which is above heavy ion LET threshold no matter whether the SRAM is non-hardened 6T SRAM or radiation-hardened double dual interlocked cells (DICE) SRAM. When the LET value is lower than the LET threshold of MCU, the SEU only manifests single cell upset, the SEU cross section increases with the decrease of voltage. The lower the LET value, the higher the SEU sensitivity to the voltage variation is. Lowering the voltage has no evident influence on SEU cross section while the LET value is above the LET threshold of MCU. Moreover, the reduction of the voltage can result in a decrease in the highest-order MCU event cross section due to the decrease of charge collection efficiency of the outer sub-sensitive volume within a certain voltage range. With further scaling the feature size of devices down, it is suggested that the dependence of SEU on voltage variation should be paid special attention to for heavy ions with very low LET or the other particles with very low energy for nanometer commercial off-the-shelf (COTS) SRAM.

Key words: supply voltage, single event upsets, multiple-cell upsets, 65-nm SRAM, double DICE SRAM