中国物理B ›› 2021, Vol. 30 ›› Issue (4): 48503-.doi: 10.1088/1674-1056/abcf45

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  • 收稿日期:2020-09-01 修回日期:2020-10-20 接受日期:2020-12-01 出版日期:2021-03-16 发布日期:2021-03-24

Novel Si/SiC heterojunction lateral double-diffused metal-oxide semiconductor field-effect transistor with p-type buried layer breaking silicon limit

Baoxing Duan(段宝兴)†, Xin Huang(黄鑫), Haitao Song (宋海涛), Yandong Wang(王彦东), and Yintang Yang(杨银堂)   

  1. 1 Key Laboratory of the Ministry of Education for Wide Band-Gap Semiconductor Materials and Devices, School of Microelectronics, Xidian University, Xi'an 710071, China
  • Received:2020-09-01 Revised:2020-10-20 Accepted:2020-12-01 Online:2021-03-16 Published:2021-03-24
  • Contact: †Corresponding author. E-mail: bxduan@163.com
  • Supported by:
    Project supported in part by the Science Foundation for Distinguished Young Scholars of Shaanxi Province, China (Grant No. 2018JC-017) and the 111 Project (Grant No. B12026).

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Abstract: A novel silicon carbide (SiC) on silicon (Si) heterojunction lateral double-diffused metal-oxide semiconductor field-effect transistor with p-type buried layer (PBL Si/SiC LDMOS) is proposed in this paper for the first time. The heterojunction has breakdown point transfer (BPT) characteristics, and the BPT terminal technology is used to increase the breakdown voltage (BV) of Si/SiC LDMOS with the deep drain region. In order to further optimize the surface lateral electric field distribution of Si/SiC LDMOS with the deep drain region, the p-type buried layer is introduced in PBL Si/SiC LDMOS. The vertical electric field is optimized by Si/SiC heterojunction and the surface lateral electric field is optimized by the p-type buried layer, which greatly improves the BV of device and alleviates the relationship between BV and specific on-resistance (R on,sp). Through TCAD simulation, when the drift region length is 20 μ m, the BV is significantly improved from 249 V for the conventional Si LDMOS to 440 V for PBL Si/SiC LDMOS, increased by 77%; And the BV is improved from 384 V for Si/SiC LDMOS with the deep drain region to 440 V for the proposed structure, increased by 15%. The figure-of-merit (FOM) of the Si/SiC LDMOS with the deep drain region and PBL Si/SiC LDMOS are 4.26 MW/cm2 and 6.37 MW/cm2, respectively. For the PBL Si/SiC LDMOS with the drift length of 20 μ m, the maximum FOM is 6.86 MW/cm2. The PBL Si/SiC LDMOS breaks conventional silicon limit.

Key words: Si/SiC heterojunction, LDMOS, breakdown voltage, specific on-resistance

中图分类号:  (Semiconductor-device characterization, design, and modeling)

  • 85.30.De
85.30.Tv (Field effect devices) 73.40.Qv (Metal-insulator-semiconductor structures (including semiconductor-to-insulator)) 73.40.Lq (Other semiconductor-to-semiconductor contacts, p-n junctions, and heterojunctions)