中国物理B ›› 2020, Vol. 29 ›› Issue (12): 128501-.doi: 10.1088/1674-1056/abaee4

• INTERDISCIPLINARY PHYSICS AND RELATED AREAS OF SCIENCE AND TECHNOLOGY • 上一篇    下一篇

  

  • 收稿日期:2020-05-01 修回日期:2020-08-01 接受日期:2020-08-13 出版日期:2020-12-01 发布日期:2020-12-02

PBTI stress-induced 1/ f noise in n-channel FinFET

Dan-Yang Chen(陈丹旸)1, Jin-Shun Bi(毕津顺)1,2,†, Kai Xi(习凯)2, and Gang Wang(王刚)3   

  1. 1 University of Chinese Academy of Sciences, Beijing 100049, China; 2 Institute of Microelectronics of the Chinese Academy of Sciences, Beijing 100029, China; 3 Semiconductor Manufacturing International Corporation, Shanghai 201203, China
  • Received:2020-05-01 Revised:2020-08-01 Accepted:2020-08-13 Online:2020-12-01 Published:2020-12-02
  • Contact: Corresponding author. E-mail: bijinshun@ime.ac.cn
  • Supported by:
    Project supported by the National Natural Science Foundation of China (Grant No. 61634008).

Abstract: The influence of positive bias temperature instability (PBTI) on 1/f noise performance is systematically investigated on n-channel fin field-effect transistor (FinFET). The FinFET with long and short channel (L=240 nm, 16 nm respectively) is characterized under PBTI stress from 0 s to 104 s. The 1/f noise features are analyzed by using the unified physical model taking into account the contributions from the carrier number and channel mobility fluctuations. The I d-V g, I d-V d, I g-V g tests are conducted to support and verify the physical analysis in the PBTI process. It is found that the influence of the channel mobility fluctuations may not be neglected. Due to the mobility degradation in a short-channel device, the noise level of the short channel device also degrades. Trapping and trap generation regimes of PBTI occur in high-k layer and are identified based on the results obtained for the gate leakage current and 1/f noise.

Key words: PBTI, 1/f noise, FinFET, mobility fluctuation

中图分类号:  (Microcircuit quality, noise, performance, and failure analysis)

  • 85.40.Qx
85.30.-z (Semiconductor devices) 85.30.De (Semiconductor-device characterization, design, and modeling) 85.35.-p (Nanoelectronic devices)