Analysis of tail bits generation of multilevel storage in resistive switching memory

doi:10.1088/1674-1056/27/11/118501

中国物理B ›› 2018, Vol. 27 ›› Issue (11): 118501-118501.doi: 10.1088/1674-1056/27/11/118501

• INTERDISCIPLINARY PHYSICS AND RELATED AREAS OF SCIENCE AND TECHNOLOGY • 上一篇下一篇

Analysis of tail bits generation of multilevel storage in resistive switching memory

1 School of Microelectronics, University of Chinese Academy of Sciences, Beijing 100049, China;
2 Laboratory of Nano-Fabrication and Novel Devices Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China

收稿日期:2018-08-23 修回日期:2018-10-19 出版日期:2018-11-05 发布日期:2018-11-05
通讯作者: Xiaoxin Xu, Hangbing Lv E-mail:xuxiaoxin@ime.ac.cn;lvhangbing@ime.ac.cn
基金资助:
Project supported by the Ministry of Science and Technology of China (Grant Nos. 2016YFA0203800, 2016YFA0201803, and 2018YFB0407502), the National Natural Science Foundation of China (Grant Nos. 61522408, 61334007, and 61521064), Beijing Municipal Science & Technology Commission Program, China (Grant No. Z161100000216153), and Huawei Data Center Technology Laboratory.

Analysis of tail bits generation of multilevel storage in resistive switching memory

Jing Liu(刘璟)^1,2, Xiaoxin Xu(许晓欣)^1,2, Chuanbing Chen(陈传兵)^1,2, Tiancheng Gong(龚天成)^1,2, Zhaoan Yu(余兆安)², Qing Luo(罗庆)², Peng Yuan(袁鹏)^1,2, Danian Dong(董大年)², Qi Liu(刘琦)², Shibing Long(龙世兵)², Hangbing Lv(吕杭炳)², Ming Liu(刘明)²

1 School of Microelectronics, University of Chinese Academy of Sciences, Beijing 100049, China;
2 Laboratory of Nano-Fabrication and Novel Devices Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China

Received:2018-08-23 Revised:2018-10-19 Online:2018-11-05 Published:2018-11-05
Contact: Xiaoxin Xu, Hangbing Lv E-mail:xuxiaoxin@ime.ac.cn;lvhangbing@ime.ac.cn
Supported by:
Project supported by the Ministry of Science and Technology of China (Grant Nos. 2016YFA0203800, 2016YFA0201803, and 2018YFB0407502), the National Natural Science Foundation of China (Grant Nos. 61522408, 61334007, and 61521064), Beijing Municipal Science & Technology Commission Program, China (Grant No. Z161100000216153), and Huawei Data Center Technology Laboratory.

摘要/Abstract

摘要：

The tail bits of intermediate resistance states (IRSs) achieved in the SET process (IRS^S) and the RESET process (IRS^R) of conductive-bridge random-access memory were investigated. Two types of tail bits were observed, depending on the filament morphology after the SET/RESET operation. (i) Tail bits resulting from lateral diffusion of Cu ions introduced an abrupt increase of device resistance from IRS to ultrahigh-resistance state, which mainly happened in IRS^S. (ii) Tail bits induced by the vertical diffusion of Cu ions showed a gradual shift of resistance toward lower value. Statistical results show that more than 95% of tail bits are generated in IRS^S. To achieve a reliable IRS for multilevel cell (MLC) operation, it is desirable to program the IRS in RESET operation. The mechanism of tail bit generation that is disclosed here provides a clear guideline for the data retention optimization of MLC resistive random-access memory cells.

关键词: resistive random-access memory (RRAM), multilevel cell, tail bits

Abstract:

Key words: resistive random-access memory (RRAM), multilevel cell, tail bits

中图分类号: (Semiconductor-device characterization, design, and modeling)

85.30.De

83.85.Ns (Data analysis (interconversion of data computation of relaxation and retardation spectra; time-temperature superposition, etc.)) 85.40.Qx (Microcircuit quality, noise, performance, and failure analysis)

刘璟, 许晓欣, 陈传兵, 龚天成, 余兆安, 罗庆, 袁鹏, 董大年, 刘琦, 龙世兵, 吕杭炳, 刘明. Analysis of tail bits generation of multilevel storage in resistive switching memory[J]. 中国物理B, 2018, 27(11): 118501-118501.

Jing Liu(刘璟), Xiaoxin Xu(许晓欣), Chuanbing Chen(陈传兵), Tiancheng Gong(龚天成), Zhaoan Yu(余兆安), Qing Luo(罗庆), Peng Yuan(袁鹏), Danian Dong(董大年), Qi Liu(刘琦), Shibing Long(龙世兵), Hangbing Lv(吕杭炳), Ming Liu(刘明). Analysis of tail bits generation of multilevel storage in resistive switching memory[J]. Chin. Phys. B, 2018, 27(11): 118501-118501.

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Analysis of tail bits generation of multilevel storage in resistive switching memory

Analysis of tail bits generation of multilevel storage in resistive switching memory

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